FPGA與CPLD實(shí)驗(yàn)報(bào)告

1、2FPGA與CPLD實(shí)驗(yàn)報(bào)告159030004 楊文忠實(shí)驗(yàn)一、正弦波的產(chǎn)生一、實(shí)驗(yàn)?zāi)康模? 學(xué)習(xí)Quartus II的使用；2 掌握宏單元模塊定制ROM；3 掌握VHDL語(yǔ)言中的元件例化；4 掌握VHDL語(yǔ)言中的計(jì)數(shù)器的設(shè)計(jì)；5. 掌握SignalTap II的使用。二、實(shí)驗(yàn)條件：1. 裝有Quartus II 13.0的電腦一臺(tái)；2. EP4CE15F17C8實(shí)驗(yàn)開(kāi)發(fā)板一套。三、實(shí)驗(yàn)原理：1.使用查表的方式計(jì)算正弦值，使用MATLAB產(chǎn)生ROM所需的正弦波mif文件；2.程序中根據(jù)計(jì)數(shù)器的值進(jìn)行查表輸出，并用modelsim和SignalTap II觀察輸出的結(jié)果。3.使用MATLAB產(chǎn)生m

2、if文件的程序如下：WIDTH=8;DEPTH=1024;ADDRESS_RADIX=DEC;DATA_RADIX=DEC;CONTENT BEGIN0:128;1:129;2:130;（數(shù)據(jù)略去）1021:126;1022:126;1023:127;End;保存為mif格式文件，或者直接使用Mif_Maker2010產(chǎn)生mif文件。四、實(shí)驗(yàn)內(nèi)容：1. 使用宏單元模塊定制ROM，操作步驟如下：Tools -> MegaWizars Plug-In Managerpage 1 -> Create a new custom megafunction variation -> Ne

3、xt -> MegaWizars Plug-In Managerpage 2a -> Installed Plug-In -> I/O -> Memory Complier -> ROM:1-PORT 設(shè)置好參數(shù)后，將定制的Files添加到工程中，調(diào)用Modelsim觀察正選波形，觀察之前需設(shè)計(jì)相應(yīng)參數(shù)，時(shí)鐘設(shè)置為100ns。2.使用SignalTap II邏輯分析儀分析FPGA產(chǎn)生的正弦波信號(hào), SignalTap II的使用步驟如下：Tools -> SignalTap II Logic Analyzer -> 設(shè)置好之后，直接點(diǎn)擊運(yùn)行即可。五、實(shí)

4、驗(yàn)總結(jié)：通過(guò)本次實(shí)驗(yàn)學(xué)會(huì)了怎么使用使用宏單元模塊定制ROM，并學(xué)會(huì)了如何使SignalTap II。8六、實(shí)驗(yàn)代碼：library ieee; -正弦信號(hào)發(fā)生器源文件use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity sinwave is port (clk:in std_logic; -信號(hào)源時(shí)鐘 dout:out std_logic_vector(7 downto 0);-8位波形數(shù)據(jù)輸出end;architecture dacc of sinwave iscomponent data_rom PORT(ad

5、dress: IN STD_LOGIC_VECTOR (9 DOWNTO 0);-10位地址信號(hào)clock: IN STD_LOGIC := '1'q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);end component;signal q1:std_logic_vector(9 downto 0):="0000000000"-設(shè)定內(nèi)部節(jié)點(diǎn)作為地址計(jì)算器beginprocess(clk)beginif clk'event and clk ='1' then q1<=q1+1;-q1作為地址發(fā)生器計(jì)算器

6、end if;end process;u1:data_rom port map(address=>q1,q=>dout,clock=>clk);-例化end;實(shí)驗(yàn)二、數(shù)字鐘的設(shè)計(jì)一、實(shí)驗(yàn)?zāi)康模? 熟練掌握Quartus II的使用；2 掌握宏單元模塊定制ROM；3 掌握VHDL語(yǔ)言中的元件例化；4 掌握VHDL語(yǔ)言中的數(shù)字鐘的設(shè)計(jì)；5. 練習(xí)使用VHDL寫(xiě)狀態(tài)機(jī)程序。二、實(shí)驗(yàn)條件：1. 裝有Quartus II 13.0的電腦一臺(tái)；2. EP4CE15F17C8實(shí)驗(yàn)開(kāi)發(fā)板一套。三、實(shí)驗(yàn)原理：1.EP4CE15F17C8開(kāi)發(fā)板的系統(tǒng)時(shí)鐘是50MHz，通過(guò)分頻方式產(chǎn)生1Hz的標(biāo)準(zhǔn)

7、秒脈沖，通過(guò)把三個(gè)計(jì)數(shù)器級(jí)聯(lián)，分別對(duì)電子鐘的秒分時(shí)進(jìn)行計(jì)數(shù)，計(jì)數(shù)器的模分別為60,60,24；2.對(duì)計(jì)數(shù)結(jié)果進(jìn)行二進(jìn)制到8421BCD碼的轉(zhuǎn)換，通過(guò)譯碼器把BCD碼轉(zhuǎn)換成七段碼，顯示是通過(guò)位碼控制來(lái)進(jìn)行動(dòng)態(tài)顯示的；3.本開(kāi)發(fā)板使用的按鍵是獨(dú)立式按鍵，總共有六個(gè)按鍵，上下鍵完成狀態(tài)間的切換，左右鍵完成數(shù)字的加減，中間鍵為確認(rèn)鍵，還有一個(gè)單獨(dú)的復(fù)位鍵；5.通過(guò)按鍵來(lái)完成當(dāng)前時(shí)間和鬧鐘的時(shí)間調(diào)整。四、實(shí)驗(yàn)內(nèi)容：1.計(jì)數(shù)器的設(shè)計(jì)在本次實(shí)驗(yàn)中使用了較多的計(jì)數(shù)器，通過(guò)編寫(xiě)通用計(jì)數(shù)器，再在主程序中多次例化，以達(dá)到精簡(jiǎn)代碼的目的。本計(jì)數(shù)器定義了置數(shù)使能和置數(shù)值輸入口來(lái)完成當(dāng)前時(shí)鐘時(shí)間的調(diào)節(jié)。時(shí)鐘的位數(shù)和模值可

8、通過(guò)具體的例化原件來(lái)進(jìn)行初始化。entity counter isgeneric (bitwidth:integer:=4;moda:integer:=12);port (clk,en,en_set:in std_logic;d :in std_logic_vector(bitwidth-1 downto 0); cout:out std_logic; counterout :out std_logic_vector(bitwidth-1 downto 0);end entity;計(jì)數(shù)器的cout是計(jì)數(shù)進(jìn)位端，作為下一級(jí)計(jì)數(shù)器的計(jì)數(shù)使能端，此處需要注意本級(jí)的進(jìn)位端不能作為下一級(jí)的時(shí)鐘信號(hào)使，因

9、為進(jìn)位端的毛刺會(huì)使計(jì)數(shù)結(jié)果出現(xiàn)錯(cuò)誤。2.按鍵去抖程序的設(shè)計(jì)實(shí)驗(yàn)中需要對(duì)按鍵進(jìn)行消抖處理，消抖的程序是直接采用計(jì)數(shù)器計(jì)數(shù)的形式，等計(jì)數(shù)器達(dá)到一定的值時(shí)，將相應(yīng)的按鍵使能信號(hào)置為有效位。設(shè)置計(jì)數(shù)器的最大計(jì)數(shù)值為5000000，當(dāng)按鍵按下時(shí)間到100ms時(shí)，將按鍵使能信號(hào)置位。調(diào)節(jié)時(shí)間和鬧鐘時(shí)間的程序采用狀態(tài)機(jī)的方法設(shè)計(jì)。狀態(tài)轉(zhuǎn)換如下現(xiàn)態(tài)key_rst_enkey_ok_enkey_up_enkey_down_enkey_left_enkey_right_enS0S5S1S0S0S0S0S1S5S5S4S2S1S1S2S5S5S1S3S2S2S3S5S5S2S4S3S3S4S5S5S3S1S4S4S

10、5S0S0是空閑狀態(tài)，在沒(méi)有按鍵按下時(shí)在此狀態(tài)，S1是分鐘調(diào)節(jié)狀態(tài)，S2是小時(shí)調(diào)節(jié)狀態(tài)，S3是鬧鐘分鐘調(diào)節(jié)狀態(tài)，S4是鬧鐘小時(shí)調(diào)節(jié)狀態(tài)，S5是置數(shù)使能端使能狀態(tài)，此狀態(tài)停留一個(gè)系統(tǒng)時(shí)鐘后自動(dòng)返回S0狀態(tài)。3. 譯碼器的設(shè)計(jì) 本設(shè)計(jì)的譯碼器包括兩類(lèi)譯碼器：（1）將二進(jìn)制數(shù)轉(zhuǎn)換成8421BCD碼；（2）將BCD碼轉(zhuǎn)換成七段碼。4.在調(diào)節(jié)時(shí)間的時(shí)候?yàn)榱孙@示現(xiàn)在正在調(diào)節(jié)的時(shí)間，在程序中加入顯示控制端，顯示控制端共四位，說(shuō)明如下：調(diào)節(jié)內(nèi)容disply_ctrl分鐘調(diào)節(jié)1010小時(shí)調(diào)節(jié)1011鬧鈴分鐘調(diào)節(jié)1110鬧鈴小時(shí)調(diào)節(jié)1111當(dāng)正在調(diào)節(jié)時(shí)間時(shí)，讓秒顯示00，當(dāng)調(diào)節(jié)鬧鈴時(shí)間時(shí)，讓秒顯示55，在主程序中

11、顯示控制程序如下：if disply_ctrl(3 downto 2)="10" then-有鍵按下hour_display<=hour_set;minute_display<=minute_set;second_display<="000000"elsif disply_ctrl(3 downto 2)="11" thenhour_display<=hour_alarm;minute_display<=minute_alarm;second_display<="110111"e

12、lsehour_display<=hour;minute_display<=minute;second_display<=second;end if;為了便于觀察正在設(shè)置的是分鐘還是小時(shí)，使正在設(shè)置的部分以2Hz的頻率閃爍顯示，處理方法如下：case cnt8 iswhen "000" => if disply_ctrl(1 downto 0)="11" thenbt <= "111110" or ("11111" & clk_0_5s_duty_50 ); elsebt &l

13、t;= "111110"end if;a<=no1;when "001" => if disply_ctrl(1 downto 0)="11" thenbt <= "111101" or ("1111" & clk_0_5s_duty_50 & '1' ); elsebt <= "111101"end if;a<=no2;when "010" => if disply_ctrl(1 dow

14、nto 0)="10" thenbt <= "111011" or ("111" & clk_0_5s_duty_50 & "11" ); elsebt <= "111011"end if;a<=no3;when "011" => if disply_ctrl(1 downto 0)="10" thenbt <= "110111" or ("11" & clk_0

15、_5s_duty_50 & "111" ); elsebt <= "110111"end if;a<=no4;when "100" => bt <= "101111" a<=no5;when "101" => bt <= "011111" a<=no6;when others => bt <= "000000" a<=15;-null;end case;6.鬧鈴?fù)ㄟ^(guò)對(duì)比當(dāng)前時(shí)間和設(shè)定

16、的鬧鈴的時(shí)間，當(dāng)相同時(shí)，啟動(dòng)蜂鳴器，主要程序如下：if hour=hour_alarm and minute=minute_alarm thenbuzzer <= '1'elsebuzzer <= '0'end if;五、實(shí)驗(yàn)總結(jié)：35通過(guò)動(dòng)手完成了本實(shí)驗(yàn)的主要任務(wù)，顯示時(shí)間，調(diào)節(jié)時(shí)間，鬧鈴功能。6、 實(shí)驗(yàn)代碼計(jì)數(shù)器程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter isgeneric (bitwidth:integer:

17、=4;moda:integer:=12);port (clk,en,en_set:in std_logic;d :in std_logic_vector(bitwidth-1 downto 0); cout:out std_logic; counterout :out std_logic_vector(bitwidth-1 downto 0);end entity;architecture one of counter isbeginprocess(clk)variable temp:std_logic_vector(bitwidth-1 downto 0);beginif clk'e

18、vent and clk='1' thencout<='0'if en_set='0' then temp := d;cout<='0'elsif en='1' thenif temp < moda-1 then temp :=temp + '1'elsetemp :=(others=>'0');cout<='1'end if;end if;end if;counterout<=temp;end process;end;按鍵消抖程序

19、：library ieee;use ieee.std_logic_1164.all;entity key_detect isgeneric (N:integer:=5);port (clk : in std_logic;key_rst : in std_logic;key_ok : in std_logic;key_up : in std_logic;key_down : in std_logic;key_left : in std_logic;key_right : in std_logic;key_rst_en : out std_logic;key_ok_en : out std_log

20、ic;key_up_en : out std_logic;key_down_en : out std_logic;key_left_en : out std_logic;key_right_en : out std_logic);end entity key_detect;architecture one of key_detect issignal key_all : std_logic_vector (5 downto 0);-將輸入輸出并行操作signal key_all_en : std_logic_vector (5 downto 0);signal key_and : std_lo

21、gic;-輸入相與beginprocess(clk)variable count : integer range 0 to 500000;beginkey_all <= key_rst & key_ok & key_up & key_down & key_left & key_right;key_and <= key_rst and key_ok and key_up and key_down and key_left and key_right;if clk'event and clk='1' thenif key_

22、and='0' thenif count=N then count:=count;else count:=count+1;end if;if count=N-1 then key_all_en<=key_all;else key_all_en<="111111"end if;else count:=0;key_all_en<="111111"end if;end if;key_rst_en <= key_all_en(5);key_ok_en <= key_all_en(4);key_up_en <=

23、key_all_en(3);key_down_en <= key_all_en(2);key_left_en <= key_all_en(1);key_right_en <= key_all_en(0);end process;end architecture one;當(dāng)前時(shí)間及鬧鐘時(shí)間設(shè)置程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity time_set isport (clk : in std_logic;key_rst_en : in std_logic;

24、key_ok_en : in std_logic;key_up_en : in std_logic;key_down_en : in std_logic;key_left_en : in std_logic;key_right_en : in std_logic;minute : in std_logic_vector(5 downto 0);-當(dāng)前的時(shí)間和鬧鐘時(shí)間hour : in std_logic_vector(4 downto 0);minute_set : out std_logic_vector(5 downto 0);-分別為秒分時(shí)的設(shè)置單元hour_set : out std_

25、logic_vector(4 downto 0);minute_alarm : out std_logic_vector(5 downto 0);hour_alarm : out std_logic_vector(4 downto 0);en_set : out std_logic;disply_ctrl : out std_logic_vector(3 downto 0);end entity time_set;architecture one of time_set isconstant s0 : integer := 0;-空閑狀態(tài)constant s1 : integer := 1;-

26、設(shè)置計(jì)數(shù)時(shí)間的分鐘constant s2 : integer := 2;-設(shè)置計(jì)數(shù)時(shí)間的小時(shí)constant s3 : integer := 3;-設(shè)置鬧鐘時(shí)間的分鐘constant s4 : integer := 4;-設(shè)置鬧鐘時(shí)間的小時(shí)constant s5 : integer := 5;beginp1:process(clk)variable state : integer range 0 to 8;-當(dāng)前狀態(tài)機(jī)的狀態(tài)variable minute_set_temp : std_logic_vector(5 downto 0);-分別為秒分時(shí)的設(shè)置單元variable hour_set_

27、temp : std_logic_vector(4 downto 0);variable minute_a_set_temp : std_logic_vector(5 downto 0);variable hour_a_set_temp : std_logic_vector(4 downto 0);beginif clk'event and clk='1' thencase state iswhen s0 => en_set <= '1'-復(fù)位低電平有效if key_rst_en='0' then -有復(fù)位鍵按下minute_

28、set_temp := "000000"-對(duì)時(shí)間進(jìn)行復(fù)位hour_set_temp := "00000"minute_a_set_temp:= "000000"hour_a_set_temp := "00000"-en_set <= '0'-復(fù)位低電平有效state := s5;elsif key_ok_en='0' then -有設(shè)置鍵按下minute_set_temp := minute;-讀取當(dāng)前的時(shí)間hour_set_temp := hour;disply_ctrl &

29、lt;= "1010"-顯示控制state := s1;end if;when s1 => en_set <= '1'-復(fù)位低電平有效if key_rst_en='0' then -有復(fù)位鍵按下minute_set_temp := "000000"-對(duì)時(shí)間進(jìn)行復(fù)位hour_set_temp := "00000"minute_a_set_temp:= "000000"hour_a_set_temp := "00000"-en_set <= '

30、;0'-復(fù)位低電平有效state := s5;elsif key_ok_en='0' then-退出設(shè)置minute_set <= minute_set_temp;hour_set <= hour_set_temp;minute_alarm <= minute_a_set_temp;hour_alarm <= hour_a_set_temp;-en_set <= '0'-復(fù)位低電平有效disply_ctrl <= "0000"state := s5;elsif key_up_en='0

31、9; then-跳至鬧鐘小時(shí)設(shè)置disply_ctrl <= "1111"-顯示控制state := s4;elsif key_down_en='0' then-跳至小時(shí)設(shè)置disply_ctrl <= "1011"-顯示控制state := s2;elsif key_left_en='0' then-分鐘減1if minute_set_temp>"000000" thenminute_set_temp:= minute_set_temp-'1'elseminute_s

32、et_temp:= "000000"end if;elsif key_right_en='0' then-分鐘加1if minute_set_temp<"111011" thenminute_set_temp:= minute_set_temp+'1'elseminute_set_temp:= "000000"end if;end if;when s2 => en_set <= '1'-復(fù)位低電平有效if key_rst_en='0' then -有復(fù)位

33、鍵按下minute_set_temp := "000000"-對(duì)時(shí)間進(jìn)行復(fù)位hour_set_temp := "00000"minute_a_set_temp:= "000000"hour_a_set_temp := "00000"-en_set <= '0'-復(fù)位低電平有效state := s5;elsif key_ok_en='0' then-退出設(shè)置minute_set <= minute_set_temp;hour_set <= hour_set_temp;

34、minute_alarm <= minute_a_set_temp;hour_alarm <= hour_a_set_temp;-en_set <= '0'-復(fù)位低電平有效disply_ctrl <= "0000"state := s5;elsif key_up_en='0' then-跳至分鐘設(shè)置disply_ctrl <= "1010"-顯示控制state := s1;elsif key_down_en='0' then-跳至鬧鈴分鐘設(shè)置disply_ctrl <=

35、"1110"-顯示控制state := s3;elsif key_left_en='0' then-小時(shí)減1if hour_set_temp>"00000" thenhour_set_temp:= hour_set_temp-'1'elsehour_set_temp:= "00000"end if;elsif key_right_en='0' then-小時(shí)加1if hour_set_temp<"10111" thenhour_set_temp:= hou

36、r_set_temp+'1'elsehour_set_temp:= "00000"end if;end if;when s3 => en_set <= '1'-復(fù)位低電平有效if key_rst_en='0' then -有復(fù)位鍵按下minute_set_temp := "000000"-對(duì)時(shí)間進(jìn)行復(fù)位hour_set_temp := "00000"minute_a_set_temp:= "000000"hour_a_set_temp := "0

37、0000"-en_set <= '0'-復(fù)位低電平有效state := s5;elsif key_ok_en='0' then-退出設(shè)置minute_set <= minute_set_temp;hour_set <= hour_set_temp;minute_alarm <= minute_a_set_temp;hour_alarm <= hour_a_set_temp;-en_set <= '0'-復(fù)位低電平有效disply_ctrl <= "0000"state :=

38、s5;elsif key_up_en='0' then-跳至小時(shí)設(shè)置disply_ctrl <= "1011"-顯示控制state := s2;elsif key_down_en='0' then-跳至鬧鈴小時(shí)設(shè)置disply_ctrl <= "1111"-顯示控制state := s4;elsif key_left_en='0' then-鬧鈴分鐘減1if minute_a_set_temp>"000000" thenminute_a_set_temp:= minut

39、e_a_set_temp-'1'elseminute_a_set_temp:= "000000"end if;elsif key_right_en='0' then-鬧鈴分鐘加1if minute_a_set_temp<"111011" thenminute_a_set_temp:= minute_a_set_temp+'1'elseminute_a_set_temp:= "000000"end if;end if;when s4 => en_set <= '1

40、'-復(fù)位低電平有效if key_rst_en='0' then -有復(fù)位鍵按下minute_set_temp := "000000"-對(duì)時(shí)間進(jìn)行復(fù)位hour_set_temp := "00000"minute_a_set_temp:= "000000"hour_a_set_temp := "00000"-en_set <= '0'-復(fù)位低電平有效state := s5;elsif key_ok_en='0' then-退出設(shè)置minute_set <

41、;= minute_set_temp;hour_set <= hour_set_temp;minute_alarm <= minute_a_set_temp;hour_alarm <= hour_a_set_temp;-en_set <= '0'-復(fù)位低電平有效disply_ctrl <= "0000"state := s5;elsif key_up_en='0' then-跳至鬧鐘分鐘設(shè)置disply_ctrl <= "1110"-顯示控制state := s3;elsif key_d

42、own_en='0' then-跳至分鐘設(shè)置disply_ctrl <= "1010"-顯示控制state := s1;elsif key_left_en='0' then-鬧鈴小時(shí)減1if hour_a_set_temp>"00000" thenhour_a_set_temp:= hour_a_set_temp-'1'elsehour_a_set_temp:= "00000"end if;elsif key_right_en='0' then-鬧鈴小時(shí)加1i

43、f hour_a_set_temp<"10111" thenhour_a_set_temp:= hour_a_set_temp+'1'elsehour_a_set_temp:= "00000"end if;end if;when s5 =>state := s0;en_set <= '0'-置數(shù)使能when others =>state := s0;en_set <= '1'minute_set <= minute_set_temp;hour_set <= hour

44、_set_temp;minute_alarm <= minute_a_set_temp;hour_alarm <= hour_a_set_temp;end case;minute_set <= minute_set_temp;hour_set <= hour_set_temp;minute_alarm <= minute_a_set_temp;hour_alarm <= hour_a_set_temp;end if;end process;end architecture one;二進(jìn)制數(shù)轉(zhuǎn)8421BCD碼程序：library IEEE;use IEEE.S

45、TD_LOGIC_1164.all;entity dec_to_bcd isport(tt : in std_logic_vector(5 downto 0); led0 : out integer range 0 to 15; led1 : out integer range 0 to 15);end entity;architecture one of dec_to_bcd isbeginprocess(tt)begincase tt iswhen "000000" => led1<=0;led0<=0;-0when "000001"

46、; => led1<=0;led0<=1;-1when "000010" => led1<=0;led0<=2;-2when "000011" => led1<=0;led0<=3;-3when "000100" => led1<=0;led0<=4;-4when "000101" => led1<=0;led0<=5;-5when "000110" => led1<=0;led0<=6;

47、-6when "000111" => led1<=0;led0<=7;-7when "001000" => led1<=0;led0<=8;-8when "001001" => led1<=0;led0<=9;-9when "001010" => led1<=1;led0<=0;-10when "001011" => led1<=1;led0<=1;-11when "001100" =&

48、gt; led1<=1;led0<=2;-12when "001101" => led1<=1;led0<=3;-13when "001110" => led1<=1;led0<=4;-14when "001111" => led1<=1;led0<=5;-15when "010000" => led1<=1;led0<=6;-16when "010001" => led1<=1;led0<=7

49、;-17when "010010" => led1<=1;led0<=8;-18when "010011" => led1<=1;led0<=9;-19when "010100" => led1<=2;led0<=0;-20when "010101" => led1<=2;led0<=1;-21when "010110" => led1<=2;led0<=2;-22when "010111&quo

50、t; => led1<=2;led0<=3;-23when "011000" => led1<=2;led0<=4;-24when "011001" => led1<=2;led0<=5;-25when "011010" => led1<=2;led0<=6;-26when "011011" => led1<=2;led0<=7;-27when "011100" => led1<=2;led0&

51、lt;=8;-28when "011101" => led1<=2;led0<=9;-29when "011110" => led1<=3;led0<=0;-30when "011111" => led1<=3;led0<=1;-31when "100000" => led1<=3;led0<=2;-32when "100001" => led1<=3;led0<=3;-33when "10001

52、0" => led1<=3;led0<=4;-34when "100011" => led1<=3;led0<=5;-35when "100100" => led1<=3;led0<=6;-36when "100101" => led1<=3;led0<=7;-37when "100110" => led1<=3;led0<=8;-38when "100111" => led1<=3;

53、led0<=9;-39when "101000" => led1<=4;led0<=0;-40when "101001" => led1<=4;led0<=1;-41when "101010" => led1<=4;led0<=2;-42when "101011" => led1<=4;led0<=3;-43when "101100" => led1<=4;led0<=4;-44when "

54、101101" => led1<=4;led0<=5;-45when "101110" => led1<=4;led0<=6;-46when "101111" => led1<=4;led0<=7;-47when "110000" => led1<=4;led0<=8;-48when "110001" => led1<=4;led0<=9;-49when "110010" => led1&l

55、t;=5;led0<=0;-50when "110011" => led1<=5;led0<=1;-51when "110100" => led1<=5;led0<=2;-52when "110101" => led1<=5;led0<=3;-53when "110110" => led1<=5;led0<=4;-54when "110111" => led1<=5;led0<=5;-55when &

56、quot;111000" => led1<=5;led0<=6;-56when "111001" => led1<=5;led0<=7;-57when "111010" => led1<=5;led0<=8;-58when "111011" => led1<=5;led0<=9;-59when others => led1<=15;led0<=15;end case;end process;end architecture;BCD碼轉(zhuǎn)七

57、段碼程序：library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity decode is Port ( a : integer range 0 to 15; sg: out std_logic_vector (6 downto 0);end entity;architecture one of decode isbegin process(a)begincase a iswhen 0 => sg<="1000000"when 1 => sg<="1111001"when 2 => sg&l

58、t;="0100100"when 3 => sg<="0110000"when 4 => sg<="0011001"when 5 => sg<="0010010"when 6 => sg<="0000010"when 7 => sg<="1111000"when 8 => sg<="0000000"when 9 => sg<="0010000"when 10 => s