智力搶答器的設(shè)計(jì)與分析.ppt

第3章 智力搶答器的設(shè)計(jì)與分析,3.1 系統(tǒng)設(shè)計(jì)要求 3.2 系統(tǒng)設(shè)計(jì)方案 3.3 主要VHDL源程序 3.4 系統(tǒng)仿真/硬件驗(yàn)證 3.5 設(shè)計(jì)技巧分析 3.6 系統(tǒng)擴(kuò)展思路,3.1 系統(tǒng)設(shè)計(jì)要求,在許多比賽活動(dòng)中，為了準(zhǔn)確、公正、直觀地判斷出第一搶答者，通常設(shè)置一臺(tái)搶答器，通過(guò)數(shù)顯、燈光及音響等多種手段指示出第一搶答者。同時(shí)，還可以設(shè)置計(jì)分、犯規(guī)及獎(jiǎng)懲計(jì)錄等多種功能。本設(shè)計(jì)的具體要求是：,(1) 設(shè)計(jì)制作一個(gè)可容納四組參賽者的數(shù)字智力搶答器，每組設(shè)置一個(gè)搶答按鈕供搶答者使用。 (2) 電路具有第一搶答信號(hào)的鑒別和鎖存功能。 (3) 設(shè)置計(jì)分電路。 (4) 設(shè)置犯規(guī)電路。,3.2 系統(tǒng)設(shè)計(jì)方案,根據(jù)系統(tǒng)設(shè)計(jì)要求可知，系統(tǒng)的輸入信號(hào)有：各組的搶答按鈕A、B、C、D，系統(tǒng)清零信號(hào)CLR，系統(tǒng)時(shí)鐘信號(hào)CLK，計(jì)分復(fù)位端RST，加分按鈕端ADD，計(jì)時(shí)預(yù)置控制端LDN，計(jì)時(shí)使能端EN，計(jì)時(shí)預(yù)置數(shù)據(jù)調(diào)整按鈕TA、TB；系統(tǒng)的輸出信號(hào)有：四個(gè)組搶答成功與否的指示燈控制信號(hào)輸出口LEDA、LEDB、LEDC、LEDD，四個(gè)組搶答時(shí)的計(jì)時(shí)數(shù)碼顯示控制信號(hào)若干，搶答成功組別顯示的控制信號(hào)若干，各組計(jì)分動(dòng)態(tài)顯示的控制信號(hào)若干。,根據(jù)以上的分析，我們可將整個(gè)系統(tǒng)分為三個(gè)主要模塊：搶答鑒別模塊QDJB；搶答計(jì)時(shí)模塊JSQ；搶答計(jì)分模塊JFQ。對(duì)于需顯示的信息，需增加或外接譯碼器，進(jìn)行顯示譯碼。考慮到FPGA/CPLD的可用接口及一般EDA實(shí)驗(yàn)開(kāi)發(fā)系統(tǒng)提供的輸出顯示資源的限制，這里我們將組別顯示和計(jì)時(shí)顯示的譯碼器內(nèi)設(shè)，而將各組的計(jì)分顯示的譯碼器外接。整個(gè)系統(tǒng)的組成框圖如圖3.1所示。,圖3.1 智力搶答器的組成框圖,3.3 主要VHDL源程序,3.3.1 搶答鑒別電路QDJB的VHDL源程序 -QDJB.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY QDJB IS PORT(CLR: IN STD_LOGIC; A, B, C, D: IN STD_LOGIC; A1,B1,C1,D1: OUT STD_LOGIC; STATES: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);,END ENTITY QDJB; ARCHITECTURE ART OF QDJB IS CONSTANT W1: STD_LOGIC_VECTOR: =“0001“; CONSTANT W2: STD_LOGIC_VECTOR: =“0010“; CONSTANT W3: STD_LOGIC_VECTOR: =“0100“; CONSTANT W4: STD_LOGIC_VECTOR: =“1000“; BEGIN PROCESS(CLR,A,B,C,D) IS BEGIN,IF CLR=1 THEN STATES=“0000“; ELSIF (A=1AND B=0AND C=0AND D=0) THEN A1=1; B1=0; C1=0; D1=0; STATES=W1; ELSIF (A=0AND B=1AND C=0AND D=0) THEN A1=0; B1=1; C1=0; D1=0; STATES=W2; ELSIF (A=0AND B=0AND C=1AND D=0) THEN A1=1; B1=0; C1=1; D1=0; STATES=W3; ELSIF (A=0AND B=0AND C=0AND D=1) THEN A1=0; B1=0; C1=0; D1=1; STATES=W4; END IF; END PROCESS; END ARCHITECTURE ART;,3.3.2 計(jì)分器電路JFQ的VHDL源程序 -JFQ.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JFQ IS PORT(RST: IN STD_LOGIC; ADD: IN STD_LOGIC; CHOS: IN STD_LOGIC_VECTOR(3 DOWNTO 0); AA2,AA1,AA0,BB2,BB1,BB0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);,CC2,CC1,CC0,DD2,DD1,DD0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END ENTITY JFQ ; ARCHITECTURE ART OF JFQ IS BEGIN PROCESS(RST,ADD,CHOS) IS VARIABLE POINTS_A2,POINTS_A1: STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE POINTS_B2,POINTS_B1: STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE POINTS_C2,POINTS_C1: STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE POINTS_D2,POINTS_D1: STD_LOGIC_VECTOR(3 DOWNTO 0);,BEGIN IF (ADDEVENT AND ADD=1) THEN IF RST=1 THEN POINTS_A2: =“0001“; POINTS_A1: =“0000“; POINTS_B2: =“0001“; POINTS_B1: =“0000“; POINTS_C2: =“0001“; POINTS_C1: =“0000“; POINTS_D2: =“0001“; POINTS_D1: =“0000“; ELSIF CHOS=“0001“ THEN,IF POINTS_A1=“1001“ THEN POINTS_A1: =“0000“; IF POINTS_A2=“1001“ THEN POINTS_A2: =“0000“; ELSE POINTS_A2: =POINTS_A2+1; END IF; ELSE POINTS_A1: =POINTS_A1+1; END IF; ELSIF CHOS=“0010“ THEN,IF POINTS_B1=“1001“ THEN POINTS_B1: =“0000“; IF POINTS_B2=“1001“ THEN POINTS_B2: =“0000“; ELSE POINTS_B2: =POINTS_B2+1; END IF; ELSE POINTS_B1: =POINTS_B1+1; END IF;,ELSIF CHOS=“0100“ THEN IF POINTS_C1=“1001“ THEN POINTS_C1: =“0000“; IF POINTS_C2=“1001“ THEN POINTS_C2: =“0000“; ELSE POINTS_C2: =POINTS_C2+1; END IF; ELSE POINTS_C1: =POINTS_C1+1; END IF;,ELSIF CHOS=“1000“ THEN IF POINTS_D1=“1001“ THEN POINTS_D1: =“0000“; IF POINTS_D2=“1001“ THEN POINTS_D2: =“0000“; ELSE POINTS_D2: =POINTS_D2+1; END IF; ELSE POINTS_D1: =POINTS_D1+1;,END IF; END IF; END IF; AA2=POINTS_A2; AA1=POINTS_A1; AA0=“0000“; BB2=POINTS_B2; BB1=POINTS_B1; BB0=“0000“; CC2=POINTS_C2; CC1=POINTS_C1; CC0=“0000“; DD2=POINTS_D2; DD1=POINTS_D1; DD0=“0000“; END PROCESS; END ARCHITECTURE ART;,3.3.3 計(jì)時(shí)器電路JSQ的VHDL源程序 -JSQ.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JSQ IS PORT(CLR,LDN,EN,CLK: IN STD_LOGIC; TA,TB: IN STD_LOGIC; QA: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); QB: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);,END ENTITY JSQ; ARCHITECTURE ART OF JSQ IS SIGNAL DA: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL DB: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(TA,TB,CLR) IS BEGIN IF CLR=1 THEN DA=“0000“; DB=“0000“; ELSE,IF TA=1 THEN DA=DA+1 ; END IF; IF TB=1 THEN DB=DB+1; END IF; END IF; END PROCESS; PROCESS(CLK) IS VARIABLE TMPA: STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE TMPB: STD_LOGIC_VECTOR(3 DOWNTO 0);,BEGIN IF CLR=1 THEN TMPA: =“0000“; TMPB: =“0110“; ELSIF CLKEVENT AND CLK=1 THEN IF LDN=1 THEN TMPA: =DA; TMPB: =DB; ELSIF EN=1 THEN IF TMPA=“0000“ THEN TMPA: =“1001“; IF TMPB=“0000“ THEN TMPB: =“0110“; ELSE TMPB: =TMPB-1;,END IF; ELSE TMPA: =TMPA-1; END IF; END IF; END IF; QA=TMPA; QB=TMPB; END PROCESS; END ARCHITECTURE ART;,3.3.4 譯碼器電路YMQ的VHDL源程序 -YMQ.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY YMQ IS PORT(AIN4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT7: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); END YMQ; ARCHITECTURE ART OF YMQ IS,BEGIN PROCESS(AIN4) BEGIN CASE AIN4 IS WHEN “0000“=DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7=“1111101“; -6,WHEN “0111“=DOUT7DOUT7DOUT7DOUT7=“0000000“; END CASE; END PROCESS; END ARCHITECTURE ART;,3.4 系統(tǒng)仿真/硬件驗(yàn)證,3.4.1 系統(tǒng)的有關(guān)仿真 系統(tǒng)仿真后的結(jié)果分別如圖3.2、圖3.3、圖3.4、圖3.5所示。,圖3.2 搶答鑒別電路QDJB仿真圖,圖3.3 計(jì)分器電路JFQ仿真圖,圖3.4 計(jì)時(shí)器電路JSQ仿真圖,圖3.5 譯碼器電路YMQ仿真圖,3.4.2 系統(tǒng)的硬件驗(yàn)證 請(qǐng)讀者根據(jù)自己所擁有的實(shí)驗(yàn)設(shè)備自行完成。,3.5 設(shè)計(jì)技巧分析,(1) 在搶答鑒別電路的設(shè)計(jì)中，A、B、C、D四組搶答，理論上應(yīng)該有16種可能情況，但實(shí)際上由于芯片的反應(yīng)速度快到一定程度時(shí)，兩組以上同時(shí)搶答成功的可能性非常小，因此我們可設(shè)計(jì)成只有四種情