基于Quartus II的FPGACPLD數(shù)字系統(tǒng)設(shè)計(jì)與應(yīng)用范例的源程序

1、2-28module adder_4(cout,sum,ina,inb,cin,clk);output3:0 sum;output cout;input3:0 I na,inb; /tempa，tempb中間變量聲明input cin,clk;reg3:0 tempa,tempb,sum; reg cout;reg tempc; /tempc中間變量聲明always (posedge clk) /always clk上升沿觸發(fā)begin /阻塞語句tempa=ina;tempb=inb;tempc=cin;endalways (posedge clk) /always clk上升沿觸發(fā)begi

2、ncout,sum=tempa+tempb+tempc;endendmodule2-40 timescale 1ns/10ps module adder4_testbench; reg 3:0 ina,inb;reg cin; reg clk=0;wire 3:0 sum;wire cout;always #10 clk=clk;initial begin ina=0; repeat(20) #20 ina =$random; /隨機(jī)數(shù)ina產(chǎn)生 endinitial begin inb=0; repeat(10) #40 inb =$random; /隨機(jī)數(shù)inb產(chǎn)生 endinitial

3、begin cin=0; repeat(2) #200 cin =$random%16;/ 隨機(jī)數(shù)inc產(chǎn)生#200 $stop； endadder4 adder4_te( .clk (clk ), .sum ( sum ), .cout ( cout), .ina ( ina ), .inb ( inb ), .cin ( cin ) ); initial endmodule2-73LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SEG_7 ISPORT (SEG: IN STD_

4、LOGIC_VECTOR(3 DOWNTO 0 ); /-四位二進(jìn)制碼輸入 Q3: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );/-輸出LED七段碼END SEG_7;ARCHITECTURE ART OF SEG_7 ISBEGINPROCESS(SEG) BEGINCASE SEG ISWHEN "0000" => Q3<="0000001"-0 WHEN "0001" => Q3<="1001111"-1WHEN "0010" =>

5、Q3<="0010010"-2WHEN "0011" => Q3<="0000110"-3WHEN "0100" => Q3<="1001100" ; -4WHEN "0101" => Q3<="0100100"-5WHEN "0110" => Q3<="0100000"-6WHEN "0111" => Q3<="0001

6、111"-7WHEN "1000" => Q3<="0000000"-8WHEN "1001" => Q3<="0000100"-9WHEN OTHERS => Q3<="1111111"END CASE;END PROCESS; END ART;3-1timescale 1ns/1nsmodule Decoder2x4(A,B,EN,Z) ;input A,B,EN;output 0:3 Z;wire Abar, Bbar;assign #1 Ab

7、ar=A; / 語句1assign #1 Bbar=B; / 語句2assign #2 Z0=(Abar &Bbar&EN ) ; / 語句3assign #2 Z1=(Abar & B&EN) ; / 語句4assign #2 Z2=(A&Bbar&EN) ; / 語句5assign #2 Z3=(A&B&EN) ; / 語句6endmodule3-3module FASeq(A, B, Cin, Sum, Cout) ;input A, B, Cin ;output Sum, Cout;reg Sum, Cout;reg T1

8、, T2, T3;always(A or B or Cin) begin Sum=(AB)Cin;T1=A&Cin;T2=B&Cin;T3=A&B;Cout = (T1|T2)|T3;endendmodule3-4timescale 1ns/1nsmodule Test(Pop,Pid);output Pop,Pid;reg Pop,Pid;initialbeginPop = 0; / 語句1Pid = 0; / 語句2Pop = #5 1; / 語句3Pid = #3 1; / 語句4Pop = #6 0; / 語句5Pid = #2 0; / 語句6endendmo

9、dule3-5Module FourBitFA (FA,FB,FCin,FSum,FCout);parameter SIZE = 4;input SIZE:1 FA, FB;output SIZE:1 FS uminput FCin;input FCout;wire 1: SIZE-1 FTemp;FAStrFA1( .A(FA1), .B(FB1), .Cin(FCin) , .Sum(FSum1), .Cout(FTemp1 ) ),FA2( .A(FA2), .B(FB2), .Cin(FTemp1),.Sum(FSum2),.Cout(FTemp2) ,FA3( .A(FA3), .B

10、(FB3), .Cin(FTemp2) , .Sum(FSum3), .Cout(FTemp3 ) ),FA4( .A(FA4), .B(FB4), .Cin(FTemp3),.Sum(FSum4),.Cout(FCout) ;endmodule3.1 beginArt = 0; Art = 1;end3.2initialbeginCbn <= 0;Cbn<=1;end3.3reg 0:2 Q State;initialbeginQ State = 3b011;Q State <=3b100;$display(“Current value of Q_State is”%b,Q

11、 State) ;#5; /等待一定的時(shí)延。$display(“The delayed value of Q_State is”%,b Q State);end例3.4 begin areg = breg; creg = areg; /creg的值為breg的值。 end例3.5 fork #50 r = 'h35; #100 r = 'hE2; #150 r = 'h00; #200 r = 'hF7; #250 -> end_wave; /觸發(fā)事件end_wave Join例3.6 case ( select1:2 )result = 0;2 '

12、;b01: result = flaga; 2 'b0x: result = flagb;2 'b0z: result = flaga? 'bx : 0; 2 'b10: result = flagb;2 'bx0, result = flagb;2 'bz0: result = flagb? 'bx : 0; default: result = 'bx; endcase例3.7 case(sig) :1 'bz: $display("signal is floating");1 'bx: $d

13、isplay("signal is unknown"); default:$display("signal is %b", sig); endcase例3.8reg7:0 ir; casez(ir) 8 'b1?: instruction1(ir); 8 'b01?: instruction2(ir);8 'b00010?: instruction3(ir);8 'b000001?: instruction4(ir); endcase 例3.9reg7:0 r, mask; mask = 8'bx0x0x0x0;c

14、asex(rmask)8 'b001100xx: stat1; 8 'b1100xx00: stat2; 8 'b00xx0011: stat3; 8 'bxx001100: stat4; ;endcase 例3.10begin: init_memreg7:0 tempi;for(tempi=0;tempi<memsize;tempi=tempi+1)memorytempi=0;end例3.11parameter size = 8, longsize = 16;regsize:1 opa, opb;reglongsize:1 result;begin:mu

15、ltinteger bindex;result=0;for( bindex=1; bindex<=size; bindex=bindex+1 )if(opbbindex)result = result + (opa<<(bindex-1);end例3.12 initial begin areg=0; /初始化寄存器areg for(index=0;index<size;index=index+1) memoryindex=0; /初始化一個(gè)memory end例3.13always areg = areg;例3.14always # half_period areg =

16、 areg;4-2（1）代碼一：module and_2(y,a,b);output y;input a,b;and(y,a,b);endmodule（2）代碼二：module and_2(y,a,b);output y;input a,b;reg y;always(a,b) begin case(a,b) 2'b00:y=0; 2'b01:y=0; 2'b10:y=0; 2'b11:y=1; default:y='bx; endcase endendmodule4-6(1) 代碼一：module or_2(y,a,b);output y;input a

17、,b;or(y,a,b);endmodule(2) 代碼二：module or_2(y,a,b);output y;input a,b;reg y;always(a,b) begin case(a,b) 2'b00:y<=0; 2'b01:y<=1; 2'b10:y<=1; 2'b11:y<=1; default:y<='bx; endcase endendmodule4-10(1) 代碼一：module notput(y,a);output y;input a;not(y,a);endmodule(2) 代碼二：modul

18、e notput(y,a);output y;input a;reg y;always(a) begin case(a) 1'b0:y=1; 1'b1:y=0; default:y='bx; endcase endendmodule4-14（1）代碼一：module nand_2(y,a,b);output y;input a,b;nand(y,a,b);endmodule（2）代碼二：module nand_2(y,a,b);output y;input a,b;reg y;always(a,b) begin case(a,b) 2'b00:y=1; 2

19、9;b01:y=1; 2'b10:y=1; 2'b11:y=0; default:y='bx; endcase endendmodule4-18(1) 代碼一：module nor_2(y,a,b);output y;input a,b;nor(y,a,b);endmodule(2) 代碼二：module nor_2(y,a,b);output y;input a,b;reg y;always(a,b) begin case(a,b) 2'b00:y<=1; 2'b01:y<=0; 2'b10:y<=0; 2'b11:y

20、<=0; default:y<='bx; endcase endendmodule4-22module nora(y,a,b,c,d);output y;input a,b,c,d;assign y=(a&b|c&d);endmodule4-26(1) 代碼一：module xor_2(y,a,b);output y;input a,b;xor(y,a,b);endmodule(2) 代碼二：module xor_2(y,a,b);output y;input a,b;reg y;always(a,b) begin case(a,b) 2'b00:y

21、<=0; 2'b01:y<=1; 2'b10:y<=1; 2'b11:y<=0; default:y<='bx; endcase endendmodule4-30(1) 代碼一：module xnor_2(y,a,b);output y;input a,b;xnor(y,a,b);endmodule(2) 代碼二：module xnor_2(y,a,b);output y;input a,b;reg y;always(a,b) begin case(a,b) 2'b00:y<=1; 2'b01:y<=0;

22、 2'b10:y<=0; 2'b11:y<=1; default:y<='bx; endcase endendmodule4-33(1)代碼一：module tri_gate(dout,din,en);output dout; /信號(hào)輸入端input din,en; /信號(hào)輸入端，使能端assign dout=en?din:'dz;endmodule(2)代碼二：module tri_gate(dout,din,en);output dout;input din,en;reg dout;always if(en) dout<=din; e

23、lse dout<='bz;endmodule4-36module tri_buffer(dout,din,en);output7:0 dout; /數(shù)據(jù)輸入端input7:0 din; /數(shù)據(jù)輸出端input en; reg7:0 dout;always if(en) dout<=din; else dout<=8b 'z;endmodule4-39module tri_bibuffer(en,dr,a,b);inout7:0 a,b; /雙向數(shù)據(jù)端口input en,dr; /使能端，數(shù)據(jù)方向控制端wire 7:0 a,b; /inout類型雙向端口必須定

24、義為wire類型的變量reg7:0 a_reg,b_reg;/在always、initial語句中的賦值語句被賦值變量必須是寄存器變量，在此定義a_reg,b_reg為雙向端口a,b的緩存器always(*)begin if(dr) begin if(en) begin b_reg=a; end else begin b_reg='bz; end end else begin if(en) begin a_reg=b; end else begin a_reg='bz; end endendassign a=a_reg;assign b=b_reg;endmodule測(cè)試程序如

25、下。timescale 1ns/1nsmodule tri_bibuffer_testbench;wire 7:0 a,b;reg en;reg dr;tri_bibuffer tri_bibuffer(en,dr,a,b);initial begin #10 dr=1;en=1; force a='b11110000;/ 強(qiáng)制a作為輸入端口 #30 en=0; #30 release a; / 釋放輸入端口a #10 dr=0;en=1; force b='b00001111;/ 強(qiáng)制b作為輸入端口 #30 en=0; #30 release b; / 釋放輸入端口b end

26、 endmodule5-1module encoded8_3(x,y);input7:0 x; / 信號(hào)輸入端output2:0 y; / 信號(hào)輸出端reg 2:0 y;always (x)begincase (x7:0)8'b00000001:y2:0=3'b000;8'b00000010:y2:0=3'b001;8'b00000100:y2:0=3'b010;8'b00001000:y2:0=3'b011;8'b00010000:y2:0=3'b100;8'b00100000:y2:0=3'b1

27、01;8'b01000000:y2:0=3'b110;8'b10000000:y2:0=3'b111;endcaseendendmodule5-6module youxianencoder(y,eo,gs,i,ei);input7:0 i; /信號(hào)輸入端input ei; /輸入使能端output 2:0 y;output eo, gs;reg2:0 y;reg eo, gs;always(i,ei)begin if(ei=1) begin y2:0<=3'b111; gs<=1; eo<=1;end else begin if(i7=

28、0)beginy2:0<=3'b000; gs<=0; eo<=1;endelse if(i6=0)beginy2:0<=3'b001; gs<=0; eo<=1;endelse if(i5=0)beginy2:0<=3'b010; gs<=0; eo<=1;endelse if(i4=0)beginy2:0<=3'b011; gs<=0; eo<=1;endelse if(i3=0)beginy2:0<=3'b100; gs<=0; eo<=1;endelse i

29、f(i2=0)beginy2:0<=3'b101; gs<=0; eo<=1;endelse if(i1=0)beginy2:0<=3'b110; gs<=0; eo<=1;endelse if(i0=0)beginy2:0<=3'b111; gs<=0; eo<=1;endelse if(i7:0='b11111111)beginy2:0<=3'b111; gs<=1; eo<=0;endendendendmodule5-11module decoder3_8(y,i,g1,g2,

30、g3);output7:0 y;input2:0 i;input g1, g2, g3;reg7:0 y;always(i or g1 or g2 or g3)begin if(g1=0) y=8'b11111111; else if(g2=1) y=8'b11111111; else if(g3=1) y=8'b11111111;else begin y=8'b00000001<<a;y=y;end end endmodule5-14module bcd_decoder(y,a);output6:0 y;input3:0 a;reg6:0 y;al

31、ways(a) begin case(a3:0) 4'b0000:y6:0=7'b1111110; 4'b0001:y6:0=7'b0110000; 4'b0010:y6:0=7'b1101101; 4'b0011:y6:0=7'b1111001; 4'b0100:y6:0=7'b0110011; 4'b0101:y6:0=7'b1011011; 4'b0110:y6:0=7'b1011111; 4'b0111:y6:0=7'b1110000; 4'b1000

32、:y6:0=7'b1111111; 4'b1001:y6:0=7'b1111011; 4'b1010:y6:0=7'b1110111; 4'b1011:y6:0=7'b0001111; 4'b1100:y6:0=7'b1001110; 4'b1101:y6:0=7'b0111101; 4'b1110:y6:0=7'b1001111; 4'b1111:y6:0=7'b1000111;endcaseendendmodule5-17module mux4_1(y,d0,d1,d2,

33、d3,g,a);output y;/選擇輸出端input d0,d1,d2,d3;/4個(gè)數(shù)據(jù)源input g;/使能端input1:0 a;/兩位地址碼reg y;always (d0 or d1 or d2 or d3 or g or a)begin if(g=0) y=0;case(a1:0)2'b00:y=d0;2'b01:y=d1;2'b10:y=d2;2'b11:y=d3;default:y=0;endcase endendmodule代碼二：調(diào)用門元件實(shí)現(xiàn)的4選1 MUX。module mux4_1(y,d0,d1,d2,d3,g,a);output

34、 y;input d0,d1,d2,d3;input g;input1:0 a;wire nota1, nota0,x1,x2,x3,x4;not(nota1,a1), (nota0,a0);and(x1,d0, nota1, nota0), (x2,d1, nota1, a0), (x3,d2, a1, nota0), (x4,d3, a0, a1);or(y1,x1,x2,x3,x4);and(y,y1,g);endmodule代碼三：數(shù)據(jù)流方式描述的4選1 MUX。module mux4_1(y,d0,d1,d2,d3,g,a);output y;input d0,d1,d2,d3;in

35、put g;input1:0 a;assign y=(d0&a1&a0)|(d1&a1&a0)|(d2&a1&a0)|(d3&a1&a0)&g;endmodule代碼四：用條件運(yùn)算符描述的4選1 MUX。module mux4_1(y,d0,d1,d2,d3,g,a);output y;input d0,d1,d2,d3;input g;input1:0 a;assign y=g?(a1?(a0?d3:d2):(a0?d1:d0):0;endmodule5-20module mux8_1(y,d0,d1,d2,d3,d4,

36、d5,d6,d7,g,a);output y;/選擇輸出端input d0,d1,d2,d3,d4,d5,d6,d7;/8個(gè)數(shù)據(jù)源input g;/使能端input2:0 a;/三位地址碼reg y;always (*)begin if(g=0) y=0;elsecase(a2:0)3'b000:y=d0;3'b001:y=d1;3'b010:y=d2;3'b011:y=d3;3'b100:y=d4;3'b101:y=d5;3'b110:y=d6;3'b111:y=d7;default:y=0;endcaseendendmodul

37、e5-23代碼一：門級(jí)結(jié)構(gòu)描述的2選1 MUX。module mux2_1(out,a,b,sel);output out;input a, b, sel;not(sel_,sel);and (a1,a,sel_), (a2,b,sel);or(out,a1,a2);endmodule代碼二：行為描述的2選1 MUX。module mux2_1(out,a,b,sel);output out;input a,b,sel;reg out;always(a or b or sel)beginif (sel) out=b;else out=a;endendmodule代碼三：數(shù)據(jù)流描述的2選1 MU

38、X。module mux2_1(out,a,b,sel);output out;input a,b,sel;reg out;always(a or b or sel)beginif (sel) out=b;else out=a;endendmodule5-26module demux4(y0,y1,y2,y3,din,a);output y0,y1,y2,y3;/4個(gè)數(shù)據(jù)通道input din;/數(shù)據(jù)輸入端input1:0 a;/兩位地址碼reg y0,y1,y2,y3;always(din,a)beginy0=0; y1=0; y2=0; y3=0;case(a1:0)2'b00:y

39、0=din;2'b01:y1=din;2'b10:y2=din;2'b11:y3=din;default:;endcaseendendmodule5-29module comparator(y1,y2,y3,a,b);output y1,y2,y3;/比較結(jié)果input3:0 a,b;reg 3:0 y1,y2,y3;always (a,b)beginif(a>b)beginy1=1;y2=0;y3=0;endelse if(a=b)beginy1=0;y2=1;y3=0;endelse if(a<b)beginy1=0;y2=0;y3=1;endenden

40、dmodule5-32代碼一：采用行為描述的1位半加器。module adder(sum,cout,a,b);output sum, cout;input a,b;reg sum, cout;always(a or b)beginsum=ab;cout=a&b;endendmodule代碼二：采用行為描述的1位半加器。module adder(sum, cout,a,b);output sum,cout;input a,b;reg sum,cout;always(a or b)begincout,sum=a+b;endendmodule代碼三：采用門元件實(shí)現(xiàn)的1位半加器。module

41、adder(sum, cout,a,b);output sum,cout;input a,b;and(cout,a,b);xor(sum,a,b);endmodule代碼四：數(shù)據(jù)流方式描述的1位半加器。module adder(sum, cout,a,b);output sum, cout;input a,b;assign sum=ab;assign cout=a&b;endmodule 代碼五：采用行為描述的1位半加器。module adder(sum,cout,a,b);output sum,cout;input a,b;reg sum,cout;always(a or b)beg

42、incase(a,b)/真值表描述2'b00:begin sum=0;cout=0;end2'b01:begin sum=1;cout=0;end2'b10:begin sum=1;cout=0;end2'b11:begin sum=0;cout=1;endendcaseendendmodule5-35代碼一：行為描述的1位全加器。module full_adder(sum,cout,a,b,dcout);output sum,cout;/和數(shù)、進(jìn)位input a,b,dcout;/被加數(shù)、加數(shù)、低位進(jìn)位reg sum,cout;always (a,b,dcou

43、t)begincout,sum=a+b+dcout;endendmodule代碼二：行為描述的1位全加器。module full_adder(sum,cout,a,b,dcout);output sum,cout;/和數(shù)、進(jìn)位input a,b,dcout;/被加數(shù)、加數(shù)、低位進(jìn)位reg sum,cout;always (a,b,dcout)beginsum=(ab)dcout;cout=(a&b)|(a&dcout)|(b&dcout);endendmodule代碼三：調(diào)用門元件實(shí)現(xiàn)的1位全加器。module full_adder(sum,cout,a,b,dcout

44、);output sum,cout;/和數(shù)、進(jìn)位input a,b,dcout;/被加數(shù)、加數(shù)、低位進(jìn)位wire s1,m1,m2,m3;and(m1,a,b), (m2,b,dcout), (m3,a,dcout);xor(s1,a,b),(s, s1,dcout);or(cout,m1,m2,m3);endmodule代碼四：數(shù)據(jù)流描述的1位全加器。module full_adder(sum,cout,a,b,dcout);output sum,cout;/和數(shù)、進(jìn)位input a,b,dcout;/被加數(shù)、加數(shù)、低位進(jìn)位assign sum=abdcout;assign cout=(a&

45、amp;b)|(b&dcout)|(dcout&a);endmodule代碼五：數(shù)據(jù)流描述的1位全加器。module full_adder(sum,cout,a,b,dcout);output sum,cout;/和數(shù)、進(jìn)位input a,b,dcout;/被加數(shù)、加數(shù)、低位進(jìn)位assign cout,sum=a+b+dcout;endmodule代碼六：混合描述的1為全加器。module full_adder(sum,cout,a,b,dcout);output sum,cout;/和數(shù)、進(jìn)位input a,b,dcout;/被加數(shù)、加數(shù)、低位進(jìn)位reg cout,m1,m2

46、,m3;wire s1;xor x1(s1,a,b);/調(diào)用門元件always (a or b or dcout)beginm1=a&b;m2=dcout&b;m3=a&dcout;cout=(m1|m2)|m3;endassign sum=s1dcout;endmodule5-38module full_adder4(sum,cout,a,b,dcout);output3:0 sum;/和數(shù)output cout;/進(jìn)位標(biāo)志input 3:0 a,b;/加數(shù)和被加數(shù)input dcout;/低位進(jìn)位reg cout;reg3:0 sum;always (*)begin

47、cout,sum=a+b+dcout;endendmodule5-41module full_adder16(cout,sum,a,b,cin);output cout;parameter my_size=16;outputmy_size-1:0 sum;inputmy_size-1:0 a, b;input cin;adder my_adder(cout,sum,a,b,cin);/調(diào)用adder模塊endmodule/下面為adder模塊的代碼module adder(cout,sum,a,b,cin);parameter size=16;output cout;outputsize-1:

48、0 sum;inputsize-1:0 a, b;input cin;assigncout,sum=a+b+cin;endmodule5-44代碼一： module half_sub(dout,cout,a,b);output dout,cout;/差位、借位input a,b;/被減數(shù)、減數(shù)reg dout,cout;always (*)begindout=ab;cout=(a)&b;endendmodule代碼二： module half_sub(dout,cout,a,b);output dout,cout;/差位、借位input a,b;/被減數(shù)、減數(shù)reg dout,cout

49、;always (*)begincout,dout=a-b;endendmodule5-47module sub(dout,cout,a,b,ci);output dout,cout;/差位、借位input a,b,ci;/被減數(shù)、減數(shù)、低位借位reg dout,cout;always (*)begincout,dout=a-b-ci;endendmodule5-50module sub4(dout,cout,a,b,ci);output 3:0 dout;/差值output cout;/借位input3:0 a,b;/被減數(shù)、減數(shù)input ci;reg 3:0 dout;reg cout;

50、always (*)begincout,dout=a-b-ci;endendmodule5-53方法一：用for語句實(shí)現(xiàn)2個(gè)8位數(shù)相乘。 module mult_for(outcome,a,b);parameter size=8;input size:1 a,b;/兩個(gè)操作數(shù)output 2*size:1 outcome;/結(jié)果reg 2*size:1 outcome;integer i;always(a or b)beginoutcome=0;for(i=1;i<=size;i=i+1)/for語句if(bi) outcome=outcome+(a<<(i-1);enden

51、dmodule方法二：用repeat實(shí)現(xiàn)8位二進(jìn)制數(shù)的乘法。 module mult_for(outcome,a,b);parameter size=8;input size:1 a,b;/兩個(gè)操作數(shù)output 2*size:1 outcome;/結(jié)果reg 2*size:1 temp_a, outcome;regsize:1 temp_b;always(a or b)beginoutcome=0;temp_a=a;temp_b=b;repeat(size)/repeat語句，size為循環(huán)次數(shù)beginif(temp_b1)/如果temp_b的最低位為1，就執(zhí)行下面的加法 outcome=outcome+ temp_a; temp_a= temp_a<<1;/操作數(shù)a左移一位temp_b= temp_b>>1;/ 操作數(shù)b右移一位endendendmodule5-56module voter7(pass,vote);output pass;input6:0 vote;reg2:0 sum;integer i;reg pass;always(vote)be