STM32IAP,APP參數(shù)配置,向量表映射

1、基于MDK的STM32系列IAP和APP程序的配置很多人在做IAP程序的時候，一般都能很容易就做出來，但是在做APP的時候，卻經(jīng)常會跑飛，其中原理，大都由于MDK配置出的問題，或者是APP沒有映射向量表。向量表起始地址默認(rèn)的是 0x08000000,在IAP的程序里不用再映射，但APP的起始地址已經(jīng)不再是0x08000000，所以，必須要映射到實際的起始地址，否則當(dāng) IAP跳轉(zhuǎn)到APP的時候， 程序直接就飛了。如我的APP起始地址是0x08005400，我的映射函數(shù)是這么配置的NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x5400); NVIC_VectT

2、ab_FLASH 的值就是 0x08000000 o下面讓我們來看看IAP和APP的MDK配置，其中片子為 STM32F103RE，IAP 起始是0x08000000 ,程序大小是 0x5400字節(jié)；APP的起始地址是 0x08005400 ,程序大小 是0X7AC00，配置如下：1. IAP 的 option for target'stm3210e-evel'配置1)這里要注意的是IROM1的配置2)這里是片子的選擇配置單擊setting進(jìn)入下面的界面這里要注意Programming Algorithm 的size大小。實際上經(jīng)過測試，這個size使用片子的最大的容量也沒關(guān)系

3、，即0x00080000(512K)，也不會影響程序的運行。3)以上是大家需要配置的，以下是其它的配置，與IAP功能無關(guān)緊要，是我的配置，僅供大豕參考。Options for Target rSTI3210E-EVAL,岡Options for Target rSTI3210E-EVAL,岡Device Target | Output Listing User | C/C+ | Asm Linker Debug Utilities |Select Folder for Listings.Page idth: |79Ragg Length: |66 十|V Assembler Listing:

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16、不可與IAP有區(qū)域重疊，而且size不能超過片子的大小。 這里0X7AC00與IAP的0x5400之和，剛好是 0x80000，即512KOptions for Target r STM32LDE-EFAL1岡Devi ceT虹g色t Output | Listing | User | C/C+AsmLinker Debug Vtili ti esSTMiicroelectronics STM32F103RE(MHz): 5-Opefating system; | None |SstorrtViewef File (.Sfr):I-ICode GenerationUse Cross-Modul

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18、 for algorithm(RAM 為運算法則準(zhǔn)備的空間)的size和programming for algorithm(程序為運算準(zhǔn)備的空間)的size都是默認(rèn)的，當(dāng)然程序為運算準(zhǔn)備 的空間大小也可以改成0X7AC00，起始地址改為 0x08005400，但經(jīng)過調(diào)試效果都一樣。其它MDK的設(shè)置參照IAP的(3)點以下的說明要特別注意，稍不留神就會出問題。平時我們在建立工程的時候，可能不會 去重新映射向量表，原因是一般我們程序的起始地址都是默認(rèn)的0x08000000，但此刻的APP的起始地址是0x08005400，那么就必須重新映射了。需要注意的是，在系統(tǒng)時鐘配置好后， 馬上就做向量映射，中

19、間最好先不要做其它的配置，比如端口初始化等等，否則程序跑飛也不一定的。下面的這段代碼就是我實際的配置過程。Void Mai n( void)SystemInit();系統(tǒng)初始化NVIC_SetVectorTable(NVIC_V ectTab_FLASH, 0x5400);/向量表映射 void System In it (void)/*!< Set MSION bit */RCC->CR |= (ui nt32_t)0x00000100;/*!< Reset SW1:0, HPRE3:0, PPRE12:0, PPRE22:0, MCOSEL2:0 a nd MCOPRE2

20、:0 bits */RCC->CFGR &= (ui nt32_t)0x88FFC00C;/*!< Reset HSION, HSEON, CSSON and PLLON bits */RCC->CR &= (ui nt32_t)0xEEFEFFFE;/*!< Reset HSEBYP bit */RCC->CR &= (uin t32_t)0xFFFBFFFF;/*!< Reset PLLSRC, PLLMUL3:0 a nd PLLDIV1:0 bits */RCC->CFGR &= (ui nt32_t)0xFF0

21、2FFFF;/*!< Disable all in terrupts */RCC->CIR = 0x00000000;/* Con figure the System clock freque ncy, AHB/APBx prescalers and Flash sett ings */SetSysClock();/ SetSysClock65K();#ifdef VECT_TAB_SRAMSCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocati on in In ternal SRAM. */#els

22、eSCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocati on in In ternalFLASH. */#en difstatic void SetSysClock(void)_10 uin t32_t StartUpCou nter = 0, HSEStatus = 0;/* SYSCLK, HCLK, PCLK2 and PCLK1 con figurati on*/* En able HSE */RCC->CR |= (ui nt32_t)RCC_CR_HSEON);/* Wait till HS

23、E is ready and if Time out is reached exit */doHSEStatus = RCC->CR & RCC_CR_HSERDY;StartUpCou nter+; while(HSEStatus = 0) && (StartUpCo un ter != HSE_STARTUP_TIMEOUT);if (RCC->CR & RCC_CR_HSERDY) != RESET)HSEStatus = (ui nt32_t)0x01;elseHSEStatus = (ui nt32_t)0x00;if (HSEStatus

24、 = (ui nt32_t)0x01)/* En able 64-bit access */FLASH->ACR |= FLASH_ACR_ACC64;/* En able Prefetch Buffer */FLASH->ACR |= FLASH_ACR_PRFTEN;/* Flash 1 wait state */FLASH->ACR |= FLASH_ACR_LATENCY;/* Power e nable */RCC->APB1ENR |= RCC_APB1ENR_PWREN;/* Select the Voltage Ra nge 1 (1.8 V) */PWR->CR = PWR_CR_VOS_0;/* Wait Un til the V oltage Regulator is ready */while(PWR->CSR & PWR_CSR_VOSF) != RESET)/* HCLK = SYSCLK /1*/RCC->CFGR |= (ui nt32_t)RCC_CFGR_HPRE_DIV1;/* PCLK2 = HCLK /1*/RCC->CFGR |= (ui nt32_t)RCC_