2013年《數(shù)字邏輯設(shè)計與應用》期中試卷.doc

電子科技大學二零壹 年至二零一 學年第二學期“數(shù)字邏輯設(shè)計及應用”課程考試題（半期）（120分鐘）考試日期 2013年5月11日一二三四五六七八九十總分評卷教師I. To fill the answers in the “( )” ( 2 X 15 = 30 )1. 109.75 10 = ( )2 = ( ) 16 。2. (2713)10 = ( ) 2421 BCD.3. (-17 10)s signed-magnitude representation is ( ), and its 8-bit twos complement representation is ( ).4. If Xs signed-magnitude representation XSM is 111010, then (2X)s 8-bit signed-magnitude representation is ( ), and (X/2)s twos complement representation is ( ). 5. If the function, then the complement expression of the function F is , and its dual expression is .6CMOS three-state buffer has three-state outputs, HIGH, LOW and ( ).7If A twos-complement =01011010, B twos-complement =10001011, then whether occurs overflow of -A+B? (Yes or No) .8If the Gray code is （1110101）gray，then its corresponding binary number code is ( ).9There is a static hazard for the logic circuit realized according to the logic expression, then the corresponding logic expression with the same function but without the static hazard is ( ).10If VOLmax = 0.5 V, VOHmin = 2.8 V, VILmax = 0.8 V, VIHmin = 2.1 V for 74LS series , then DC noise margin is VNL = ( )V, VNH = ( )V.II. There is only one correct answer in the following questions.( 3 X 10=30 )1. Which is the correct one in the following statements for a logic function? ( )A. The minimal expression may be the sum of products or product of the sums B. The minimal expression is the minimal form with product of sums C. The minimal expression is the minimal form with sum of products D. The minimal expression with sum of products is the same simply with the minimal expression with product of sums2. Which of the following statements is the wrong one when perform arithmetic operations with two binary numbers? ( ) A. There is an overflow when the most significant bit (MSB) generates a carry out for the addition of two unsigned numbers. B. There is not an overflow for the addition of two complements with different MSB. C. There is an overflow when the MSB generates a carry out for the addition of two twos complements.D. The subtraction of two twos complements can be realized with adder.3. The static hazard of the combination logic circuit is caused by the reason that ( ).A. the circuit is not the most simple one B. there is many outputs for the circuit C. different gate circuits are applied to the circuit D. there is propagation delays at different signal paths in the circuit4. There is only one output is effective at the same time in which of the following devices ( ).A. 74X138 Decoder B. Seven-Segment Decoder C. Multiplexer D. 74X148 Encoder 5. The truth table of a circuit is shown in the following table, then the logic expression of this circuit is ( ).A. F=C B. F=ABC C. F=AB+AC D. F=BC+AC ABCFABCF000010000011101001001101011111116. The relationship between the logic function F1 = ABCD(2,4,5,7,9,14) and F2 = ABCD(1,6,8,10,11,13) is ( ).A. Duality B. Equivalent C. Shannons expansion D. Complement7. A priority encoder 74LS148s input is: I0-L, I1-L, I2-L, I3-L, I4-L, I5-L, I6-L, I7-L，output is Y2-L,Y1-L,Y0-L.The inputs and output are all active-low. When active-low enable input S_L=0 ,and I1-L=I5-L=I6-L =0, then Y2-L,Y1-L,Y0-L is ( ). A) 110 B) 010 C) 001 D) 101 8. In the following methods to describe a logic function, only ( ) has uniqueness.A. the logic expression B. the logic circuit diagram C. the truth table D. the waveform diagram9. The NAND gates in the case of the positive logic level is equivalent to the ( ) in the case of the negative logic level. A. the NAND gate B. the AND-OR gate C. the AND gate D. the NOR gate10. Which of the following statements is the wrong one for combination circuits? ( ) A. Outputs depend only on its current inputs B. They do not generates dynamic hazards C. They can be formed by using integrated binary decoders and NAND gatesD. They contains no feedback loopsIII. Combinational Circuit Analysis And Design: 401.Given F(A,B,C,D)= m (3,5,6,11,12,15)+d(1,7,13). Simplify the logic function F(A,B,C,D) into the minimal product expression using Karnaugh map, and write out NOR-NOR logic expression. (10)2. A combinational circuit is shown as below, assume propagation delay for each gate is equal to tpd. (10)(1) When A=B=D=0, C change from 0 to 1 or from 1 to 0, draw the timing diagram for Y1、Y2 and Y.(2) Analysis conditions that the static hazard may exit, and write out the product-of-sum expression for the hazard-free.3.A combinational circuit is shown as below, which contains a 74x151 multiplexer and a inverter with 4 inputs, 1-bit output. (10)(1) Write out the logic expression of the output F(S1,S0,A,B).(