數(shù)字電路實(shí)驗(yàn)報(bào)告

實(shí)驗(yàn)一、半加器與全加器的電路圖實(shí)現(xiàn)半加器1、半加器的電路圖——見(jiàn)圖1圖1——半加器的電路圖2、半加器仿真波形圖——見(jiàn)圖2圖2——半加器仿真波形圖3、仿真圖簡(jiǎn)析：如圖2，為半加器仿真波形圖。對(duì)應(yīng)a,b輸入波形，得到的c為進(jìn)位，s為和。如a=1，b＝0，c=0,s=1.4、半加器的VHDL語(yǔ)言為：libraryieee;useieee.std_logic_1164.all;entitytx23p31isport(a,b:instd_logic;co,so:outstd_logic);endentitytx23p31;architectureaoftx23p31isbeginso<=axorb;co<=aandb;end;全加器1、全加器的電路圖——見(jiàn)圖3圖3——全加器的電路圖2、全加器的VHDL語(yǔ)言libraryieee;useieee.std_logic_1164.all;entitytx23p3isport(ain,bin,cin:instd_logic;cout,sum:outstd_logic);endentitytx23p3;architectureaoftx23p3iscomponenttx23p31port(a,b:instd_logic;co,so:outstd_logic);endcomponent;signald,e,f:std_logic;beginu1:tx23p31portmap(a=>ain,b=>bin,co=>d,so=>e);u2:tx23p31portmap(a=>e,b=>cin,co=>f,so=>sum);cout<=dorf;end;3、全加器的RTLviewer：見(jiàn)圖4圖4——全加器的RTLviewer

實(shí)驗(yàn)二、函數(shù)發(fā)生器1、電路圖——見(jiàn)圖5圖5——函數(shù)發(fā)生器的實(shí)驗(yàn)電路圖2、函數(shù)發(fā)生器的仿真波形圖——見(jiàn)圖6圖6——函數(shù)發(fā)生器的仿真波形圖3、波形圖仿真分析：如上圖，當(dāng)a,b,c的取值為0，4，6，7時(shí)，f＝1；其他時(shí)刻，f＝0。如第一列波形，a=0,b=0,c=0,此時(shí)f=1.

實(shí)驗(yàn)三、四選一數(shù)據(jù)選擇器libraryieee;useieee.std_logic_1164.all;entitytx23w1is port(a:instd_logic_vector(1downto0); d:instd_logic_vector(3downto0); y:outstd_logic);endtx23w1;architecturemux4oftx23w1isbegin process(a,d) begin caseais when"00"=>y<=d(0); when"01"=>y<=d(1); when"10"=>y<=d(2); when"11"=>y<=d(3); whenothers=>y<='0'; endcase; endprocess;endmux4;圖7——四選一數(shù)據(jù)選擇器波形圖

實(shí)驗(yàn)四、裁判器libraryieee;useieee.std_logic_1164.all;entitytx23w2is port(a:instd_logic_vector(2downto0); y:outstd_logic_vector(1downto0));endtx23w2;architecturemux8oftx23w2isbegin process(a) begin caseais when"000"=>y<="00"; when"001"=>y<="00"; when"010"=>y<="00"; when"011"=>y<="10"; when"100"=>y<="10"; when"101"=>y<="11"; when"110"=>y<="11"; when"111"=>y<="11"; whenothers=>y<="00"; endcase; endprocess;endmux8;圖8——裁判表決器實(shí)驗(yàn)五、50M分頻器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitytx23w3isport(clk:instd_logic;clear:instd_logic;clk_out:outstd_logic);endtx23w3;architectureaoftx23w3issignaltmp:integerrange0to50000000;beginp1:process(clear,clk)beginifclear='0'thentmp<=0;elsifclk'eventandclk='1'theniftmp=49999999thentmp<=0;elsetmp<=tmp+1;endif;endif;endprocessp1;p2:process(clk,tmp)beginif(clk'eventandclk='1')theniftmp>=25000000thenclk_out<='1';elseclk_out<='0';endif;endif;endprocessp2;enda;

實(shí)驗(yàn)六、七段熒光屏數(shù)碼顯示學(xué)號(hào)libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitiytx23h1isport( clk:instd_logic; seg:outstd_logic_vector(6downto0); cat:outstd_logic_vector(5downto0));endtx23h1;architectureaoftx23h1is signaltmp:integerrange0to5; signalclk_tmp:integerrange0to100000; signalclk_out:std_logic; signalmove:begin p1:process(clk)begin if(clk'eventandclk='1')then ifclk_tmp=49999then clk_tmp<=0; clk_out<=notclk_out; elseclk_tmp<=clk_tmp+1; endif; endif; endprocessp1;//進(jìn)程一：分頻系數(shù)為100000的分頻器 p2:process(clk_out) begin if(clk_out'eventandclk_out='1')then iftmp=5thentmp<=0;elsetmp<=tmp+1; endif; endif;endprocessp2; //進(jìn)程二：模制為六的計(jì)數(shù)器 p3:process(tmp) begin casetmpis when0=>seg<="0110000"; when1=>seg<="1101101"; when2=>seg<="1111110"; when3=>seg<="1111111"; when4=>seg<="1101101"; when5=>seg<="1111001"; endcase; endprocessp3;//進(jìn)程三：不同計(jì)數(shù)器的計(jì)數(shù)值時(shí)的顯示數(shù)字，從0~5為：120823p4:process(tmp)begin casetmpiswhen0=>cat<="011111";when1=>cat<="101111";when2=>cat<="110111";when3=>cat<="111011";when4=>cat<="111101";when5=>cat<="111110";//進(jìn)程四：選擇輸出的熒光屏數(shù)碼管endcase;endprocessp4;enda;

實(shí)驗(yàn)七、實(shí)現(xiàn)自己學(xué)號(hào)滾動(dòng)的七段熒光屏數(shù)碼顯示libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitytx23h2is port(clk:instd_logic; seg:outstd_logic_vector(6downto0); cat:outstd_logic_vector(5downto0));endtx23h2;architectureaoftx23h2is signalcnt1:integerrange0to49999; signalcnt2:integerrange0to499; signalclk_tmp1:std_logic; signalclk_tmp2:std_logic; signalq_tmp1:integerrange0to5; signalq_tmp2:integerrange0to5;begin p1:process(clk) begin if(clk'eventandclk='1')then ifcnt1=49999then cnt1<=0; clk_tmp1<=notclk_tmp1; else cnt1<=cnt1+1; endif; endif; endprocessp1;//分頻系數(shù)為100000的分頻器 p2:process(clk_tmp1)beginif(clk_tmp1'eventandclk_tmp1='1')then ifcnt2=499then cnt2<=0; clk_tmp2<=notclk_tmp2; else cnt2<=cnt2+1; endif; endif; endprocessp2;//分頻系數(shù)為1000的分頻器，使最后的滾動(dòng)時(shí)間變?yōu)?秒 p3:process(clk_tmp1)beginif(clk_tmp1'eventandclk_tmp1='1')thenifq_tmp1=5thenq_tmp1<=0;elseq_tmp1<=q_tmp1+1;endif;endif;endprocessp3;//計(jì)數(shù)器，模制為6，第一個(gè)時(shí)鐘的時(shí)鐘沿有效p4:process(clk_tmp2)beginif(clk_tmp2'eventandclk_tmp2='1')thenifq_tmp2=5thenq_tmp2<=0;elseq_tmp2<=q_tmp2+1;endif;endif;endprocessp4;//計(jì)數(shù)器，模制為6，第二個(gè)時(shí)鐘的時(shí)鐘沿有效p5:process(q_tmp1)begincaseq_tmp1iswhen0=>seg<="0110000";//通過(guò)計(jì)數(shù)器1的值選擇要輸出的信息，為120823when1=>seg<="1101101";when2=>seg<="1111110";when3=>seg<="1111111";when4=>seg<="1101101";when5=>seg<="1111001";whenothers=>seg<="1111111";endcase;endprocessp5;p6:process(q_tmp1,q_tmp2)begincase(q_tmp1+q_tmp2)rem6is//q_tmp1+q_tmp2為兩個(gè)計(jì)數(shù)器的計(jì)數(shù)值之和，模when0=>cat<="011111";//六之后的數(shù)值進(jìn)行循環(huán)，用余數(shù)選擇熒光數(shù)碼管when1=>cat<="101111";//實(shí)現(xiàn)學(xué)號(hào)的滾動(dòng)輸出，這一步是本電路的核心；when2=>cat<="110111";when3=>cat<="111011";when4=>cat<="111101";when5=>cat<="111110";whenothers=>cat<="000000";endcase;endprocessp6;enda;（注：為了是波形顯示有序清晰，重新修改了代碼、重新設(shè)置了分頻器的系數(shù)等參數(shù)，將顯示在數(shù)碼管上的數(shù)據(jù)改成了012345）圖9——七段熒光屏數(shù)碼顯示圖10——七段熒光屏數(shù)碼滾動(dòng)顯示波形圖

實(shí)驗(yàn)七、發(fā)光二極管走馬燈電路設(shè)計(jì)與實(shí)現(xiàn)——狀態(tài)機(jī)的設(shè)計(jì)LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYtx23h3IS PORT( clk:INSTD_LOGIC; clear:INSTD_LOGIC; swich:INSTD_LOGIC; q_out:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDtx23h3;ARCHITECTUREaOFtx23h3IS SIGNALtmp:INTEGERRANGE0TO7;//定義結(jié)構(gòu)體內(nèi)部信號(hào)為從0-7的整型SIGNALe:STD_LOGIC; COMPONENTdiv50m//加入50分頻 PORT(clk_in:INSTD_LOGIC; clk_out:OUTSTD_LOGIC); ENDCOMPONENT;BEGINu1:div50mPORTMAP(clk_in=>clk,clk_out=>e); p1:PROCESS(e) BEGIN IFe'eventANDe='1'THEN//檢測(cè)到時(shí)鐘的上升沿 IFtmp=7THEN tmp<=0; ELSE tmp<=tmp+1;//信號(hào)依次改變 ENDIF; ENDIF;ENDPROCESSp1;//進(jìn)