DES算法的verilog實(shí)現(xiàn)

1、精選文檔 EDA試驗(yàn)報(bào)告一、實(shí)驗(yàn)項(xiàng)目名稱 DES算法二、實(shí)驗(yàn)?zāi)康呐c要求1.掌握DES的原理和設(shè)計(jì)方法。2.了解QuartusII硬件電路設(shè)計(jì)流程,學(xué)會(huì)利用Modelsim進(jìn)行仿真。3.加深對(duì)自頂向下設(shè)計(jì)和分模塊化的了解，學(xué)會(huì)模塊化的設(shè)計(jì)方法。三、實(shí)驗(yàn)步驟（一）.DES算法原理DES算法為密碼體制中的對(duì)稱密碼體制，又被稱為美國數(shù)據(jù)加密標(biāo)準(zhǔn)，是1972年美國IBM公司研制的對(duì)稱密碼體制加密算法。 明文按64位進(jìn)行分組，密鑰長64位，密鑰事實(shí)上是56位參與DES運(yùn)算(第8、16、24、32、40、48、56、64位是校驗(yàn)位， 使得每個(gè)密鑰都有奇數(shù)個(gè)1)分組后的明文組和56位的密鑰按位替代或交換的方法

2、形成密文組的加密方法。其入口參數(shù)有三個(gè):key、data、mode。key為加密解密使用的密鑰，data為加密解密的數(shù)據(jù)，mode為其工作模式。當(dāng)模式為加密模式時(shí)，明文按照64位進(jìn)行分組，形成明文組，key用于對(duì)數(shù)據(jù)加密，當(dāng)模式為解密模式時(shí)，key用于對(duì)數(shù)據(jù)解密。實(shí)際運(yùn)用中，密鑰只用到了64位中的56位，這樣才具有高的安全性。DES算法把64位的明文輸入塊變?yōu)?4位的密文輸出塊，它所使用的密鑰也是64位，整個(gè)算法的主流程圖如下:（二）、VerilogHDL實(shí)現(xiàn)原理 擬采用模塊化設(shè)計(jì)思想，根據(jù)DES算法的流程分模塊設(shè)計(jì)實(shí)現(xiàn)各模塊，自頂向下最終實(shí)現(xiàn)DES加密算法。各模塊功能及實(shí)現(xiàn)如下所示：1.整體

3、結(jié)構(gòu)框架搭建，實(shí)現(xiàn)總體功能 module DES(input clk, input des_enable, input reset, input des_mode, input 1:64 data_i, input 1:64 key_i, output wire 1:64 data_o, output ready_o); wire 3:0 inter_num_curr; wire 1:32 R_i_var, L_i_var; wire 1:56 Key_i_var_out; wire 1:64 data_o_var_t; wire 1:32 R_i, L_i; wire 1:32 R_o, L

4、_o; wire 1:56 Key_o; wire 1:28 C0, D0; IP IP1(.in(data_i), .L_i_var(L_i_var), .R_i_var(R_i_var); IP_ni IP_ni(.in(data_o_var_t), .out(data_o); pc_1 pc_1(.key_i(key_i), .C0(C0), .D0(D0); /F(R,K) des_f des_f1(.clk(clk), .reset(reset), .des_mode(des_mode), .inter_num_i(inter_num_curr), .R_i(R_i), .L_i(L

5、_i), .Key_i(Key_i_var_out), .R_o(R_o), .L_o(L_o), .Key_o(Key_o); /contral 16 F(R,K) contrl contrl1(.data_o_var_t(data_o_var_t), .inter_num_curr(inter_num_curr), .Key_i_var_out(Key_i_var_out), .R_i(R_i), .L_i(L_i), .ready_o(ready_o), .L_o(L_o), .R_o(R_o), .R_i_var(R_i_var), .L_i_var(L_i_var), .Key_o(

6、Key_o), .C0(C0), .D0(D0), .clk(clk), .reset(reset), .des_enable(des_enable); endmodule module IP(input 1:64 in, output 1:32 L_i_var, output 1:32 R_i_var); assign L_i_var, R_i_var = in58,in50,in42,in34,in26,in18,in10,in2, in60,in52,in44,in36,in28,in20,in12,in4, in62,in54,in46,in38,in30,in22,in14,in6,

7、 in64,in56,in48,in40,in32,in24,in16,in8, in57,in49,in41,in33,in25,in17,in9,in1, in59,in51,in43,in35,in27,in19,in11,in3, in61,in53,in45,in37,in29,in21,in13,in5, in63,in55,in47,in39,in31,in23,in15,in7; endmodulemodule IP_ni(input 1:64 in, output 1:64 out); assign out = in40,in8,in48,in16,in56,in24,in6

8、4,in32, in39,in7,in47,in15,in55,in23,in63,in31, in38,in6,in46,in14,in54,in22,in62,in30, in37,in5,in45,in13,in53,in21,in61,in29, in36,in4,in44,in12,in52,in20,in60,in28, in35,in3,in43,in11,in51,in19,in59,in27, in34,in2,in42,in10,in50,in18,in58,in26, in33,in1,in41,in9,in49,in17,in57,in25; endmodule3.圈子

9、秘鑰的生成module key_get(input 1:56 pre_key, input des_mode, input 3:0 inter_num, output wire 1:48 new_key, output reg 1:56 out_key); reg pre_key_0, pre_key_1; reg 1:56 pre_key_var; always (*) begin if(des_mode = 1'b0) begin case(inter_num) 4'd0, 4'd1, 4'd8, 4'd15: begin pre_key_var =

10、 pre_key; pre_key_0 = pre_key_var1; pre_key_var1:28 = pre_key_var1:28 << 1; pre_key_var28 = pre_key_0; pre_key_0 = pre_key_var29; pre_key_var29:56 = pre_key_var29:56 << 1; pre_key_var56 = pre_key_0; end 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd9, 4'd10, 4

11、9;d11, 4'd12, 4'd13, 4'd14: begin pre_key_var = pre_key; pre_key_1, pre_key_0 = pre_key_var1:2; pre_key_var1:28 = pre_key_var1:28 << 2; pre_key_var27:28 = pre_key_1, pre_key_0; pre_key_1, pre_key_0 = pre_key_var29:30; pre_key_var29:56 = pre_key_var29:56 << 2; pre_key_var55:56

12、 = pre_key_1, pre_key_0; end endcase end else begin case(inter_num) 4'd0: pre_key_var = pre_key; 4'd1, 4'd8, 4'd15: begin pre_key_var = pre_key; pre_key_0 = pre_key_var28; pre_key_var1:28 = pre_key_var1:28 >> 1; pre_key_var1 = pre_key_0; pre_key_0 = pre_key_var56; pre_key_var29

13、:56 = pre_key_var29:56 >> 1; pre_key_var29 = pre_key_0; end default: begin pre_key_var = pre_key; pre_key_1, pre_key_0 = pre_key_var27:28; pre_key_var1:28 = pre_key_var1:28 >> 2; pre_key_var1:2 = pre_key_1, pre_key_0; pre_key_1, pre_key_0 = pre_key_var55:56; pre_key_var29:56 = pre_key_va

14、r29:56 >> 2; pre_key_var29:30 = pre_key_1, pre_key_0; end endcase end out_key = pre_key_var; end assign new_key = pre_key_var14,pre_key_var17,pre_key_var11,pre_key_var24,pre_key_var1,pre_key_var5, pre_key_var3,pre_key_var28,pre_key_var15,pre_key_var6,pre_key_var21,pre_key_var10, pre_key_var23,

15、pre_key_var19,pre_key_var12,pre_key_var4,pre_key_var26,pre_key_var8, pre_key_var16,pre_key_var7,pre_key_var27,pre_key_var20,pre_key_var13,pre_key_var2, pre_key_var41,pre_key_var52,pre_key_var31,pre_key_var37,pre_key_var47,pre_key_var55, pre_key_var30,pre_key_var40,pre_key_var51,pre_key_var45,pre_key

16、_var33,pre_key_var48, pre_key_var44,pre_key_var49,pre_key_var39,pre_key_var56,pre_key_var34,pre_key_var53, pre_key_var46,pre_key_var42,pre_key_var50,pre_key_var36,pre_key_var29,pre_key_var32; endmodule3.f函數(shù)的實(shí)現(xiàn)module des_f(input clk, input reset, input des_mode, input 3:0 inter_num_i, input 1:32 R_i,

17、 input 1:32 L_i, input 1:56 Key_i, output reg 1:32 R_o, output reg 1:32 L_o, output reg 1:56 Key_o); reg 1:32 next_R; /reg 31:0 R_i_var; wire 1:48 expandedR; reg 1:56 pre_key; reg 1:48 new_key_tmp; reg 3:0 inter_num; wire 1:32 p; reg 1:48 address_s; reg 1:32 Soutput; wire 1:32 Soutput_wire; wire 1:4

18、8 new_key; wire 1:56 out_key; key_get key_get(.pre_key(pre_key), .des_mode(des_mode), .inter_num(inter_num), .new_key(new_key), .out_key(out_key); s1 sbox1(.stage1_input(address_s1:6), .stage1_output(Soutput_wire1:4); s2 sbox2(.stage1_input(address_s7:12), .stage1_output(Soutput_wire5:8); s3 sbox3(.

19、stage1_input(address_s13:18), .stage1_output(Soutput_wire9:12); s4 sbox4(.stage1_input(address_s19:24), .stage1_output(Soutput_wire13:16); s5 sbox5(.stage1_input(address_s25:30), .stage1_output(Soutput_wire17:20); s6 sbox6(.stage1_input(address_s31:36), .stage1_output(Soutput_wire21:24); s7 sbox7(.s

20、tage1_input(address_s37:42), .stage1_output(Soutput_wire25:28); s8 sbox8(.stage1_input(address_s43:48), .stage1_output(Soutput_wire29:32); always (posedge clk or negedge reset) begin if(reset = 1'b0) begin R_o <= 32'd0; L_o <= 32'd0; Key_o <= 56'd0; end else begin Key_o <

21、= out_key; if(inter_num = 4'b1111) begin R_o <= R_i; L_o <= next_R; end else begin R_o <= next_R; L_o <= R_i; end end end assign expandedR =R_i32,R_i1,R_i2,R_i3,R_i4,R_i5, R_i4,R_i5,R_i6,R_i7,R_i8,R_i9, R_i8,R_i9,R_i10,R_i11,R_i12,R_i13, R_i12,R_i13,R_i14,R_i15,R_i16,R_i17, R_i16,R_i

22、17,R_i18,R_i19,R_i20,R_i21, R_i20,R_i21,R_i22,R_i23,R_i24,R_i25, R_i24,R_i25,R_i26,R_i27,R_i28,R_i29, R_i28,R_i29,R_i30,R_i31,R_i32,R_i1; assign p = Soutput16,Soutput7,Soutput20,Soutput21, Soutput29,Soutput12,Soutput28,Soutput17, Soutput1,Soutput15,Soutput23,Soutput26, Soutput5,Soutput18,Soutput31,S

23、output10, Soutput2,Soutput8,Soutput24,Soutput14, Soutput32,Soutput27,Soutput3,Soutput9, Soutput19,Soutput13,Soutput30,Soutput6, Soutput22,Soutput11,Soutput4,Soutput25; always (*) begin pre_key = Key_i; inter_num = inter_num_i; new_key_tmp = new_key; address_s = new_key_tmp expandedR; Soutput = Soutp

24、ut_wire; /? next_R = (L_ip); end endmodule5.迭代控制程序的設(shè)計(jì)與代碼module contrl(output 1:64 data_o_var_t, output reg 3:0 inter_num_curr, output reg 1:56 Key_i_var_out, output reg 1:32 R_i, L_i, output reg ready_o, input 1:32 L_o, input 1:32 R_o, input 1:32 R_i_var, L_i_var, input 1:56 Key_o, input 1:28 C0, D0

25、, input clk, reset, des_enable); reg 3:0 inter_num_next; assign data_o_var_t = (ready_o = 1'b1)?L_o,R_o:64'hzzzzzzzzzzzzzzzz; always (posedge clk or negedge reset) if(reset = 1'b0) begin inter_num_next <= 4'd0; inter_num_curr <= 4'd0; ready_o <= 1'b0; end else if(des

26、_enable) begin if(ready_o = 1'b0) inter_num_curr <= inter_num_next; end always (posedge clk or negedge reset) begin if(reset = 1'b0) ready_o <= 1'b0; else if(inter_num_curr = 4'd15) ready_o <= 1'b1; else ready_o <= 1'b0; end always (*) begin case(inter_num_curr) 4

27、'd0:begin /ready_o = 1'b0; R_i = R_i_var; L_i = L_i_var; Key_i_var_out = C0, D0; inter_num_next = 4'd1; end 4'd1: begin /ready_o = 1'b0; R_i = R_o; L_i = L_o; Key_i_var_out = Key_o; inter_num_next = 4'd2; end 4'd2: begin /ready_o = 1'b0; R_i = R_o; L_i = L_o; Key_i_va

28、r_out = Key_o; inter_num_next = 4'd3; end 4'd3: begin /ready_o = 1'b0; R_i = R_o; L_i = L_o; Key_i_var_out = Key_o; inter_num_next = 4'd4; end 4'd4: begin /ready_o = 1'b0; R_i = R_o; L_i = L_o; Key_i_var_out = Key_o; inter_num_next = 4'd5; end 4'd5: begin /ready_o = 1

29、'b0; R_i = R_o; L_i = L_o; Key_i_var_out = Key_o; inter_num_next = 4'd6; end 4'd6: begin /ready_o = 1'b0; R_i = R_o; L_i = L_o; Key_i_var_out = Key_o; inter_num_next = 4'd7; end 4'd7: begin/ready_o = 1'b0; R_i = R_o; L_i = L_o; Key_i_var_out = Key_o; inter_num_next = 4

30、9;d8; end 4'd8: begin /ready_o = 1'b0; R_i = R_o; L_i = L_o; Key_i_var_out = Key_o; inter_num_next = 4'd9; end 4'd9: begin /ready_o = 1'b0; R_i = R_o; L_i = L_o; Key_i_var_out = Key_o; inter_num_next = 4'd10; end 4'd10: begin /ready_o = 1'b0; R_i = R_o; L_i = L_o; Key

31、_i_var_out = Key_o; inter_num_next = 4'd11; end 4'd11: begin /ready_o = 1'b0; R_i = R_o; L_i = L_o; Key_i_var_out = Key_o; inter_num_next = 4'd12; end 4'd12: begin /ready_o = 1'b0; R_i = R_o;L_i = L_o; Key_i_var_out = Key_o; inter_num_next = 4'd13; end 4'd13: begin /r

32、eady_o = 1'b0; R_i = R_o; L_i = L_o; Key_i_var_out = Key_o; inter_num_next = 4'd14; end 4'd14: begin /ready_o = 1'b0; R_i = R_o; L_i = L_o; Key_i_var_out = Key_o; inter_num_next = 4'd15; end 4'd15:if(ready_o = 1'b0) begin R_i = R_o; L_i = L_o; Key_i_var_out = Key_o; /read

33、y_o = 1'b1; end endcase end endmodule 6.S盒的設(shè)計(jì)與實(shí)現(xiàn)（S1）module s1(stage1_input,stage1_output); input 5:0 stage1_input; output 3:0 stage1_output; reg 3:0 stage1_output; /BIT5 and BIT0 is ? /BIT41 is ? always ( stage1_input) begin case(stage1_input) /synopsys full_case parallel_case 0: stage1_output =

34、 4'd14; 1: stage1_output = 4'd0; 2: stage1_output = 4'd4; 3: stage1_output = 4'd15; 4: stage1_output = 4'd13; 5: stage1_output = 4'd7; 6: stage1_output = 4'd1; 7: stage1_output = 4'd4; 8: stage1_output = 4'd2; 9: stage1_output = 4'd14; 10: stage1_output = 4'd15; 11: stage1_output = 4'd2; 12: stage1_output =