VHDL點陣顯示

1、 數(shù)字電路課程設(shè)計報告 課 程：基于FPGA的點陣顯示控制器的設(shè)計學 院： 電 氣 信 息 工 程 學 院 專 業(yè)： 測控技術(shù)與儀器 班 級： 姓 名： 學 號： 合作者姓名： 日 期： 一、引言隨著我國經(jīng)濟的高速發(fā)展,對公共場合發(fā)布信息的需求日益增長，利用LED點陣滾動顯示漢字的出現(xiàn)正好適應(yīng)了這一市場需求，已經(jīng)成為信息傳播的一種重要手段。采用傳統(tǒng)方法設(shè)計的漢字滾動顯示器，通常需要使用單片機、存儲器和制約邏輯電路來進行PCB板級的系統(tǒng)集成。盡管這種方案有單片機軟件的支持較為靈活，但是由于受硬件資源的限制，未來對設(shè)計的變更和升級，總是難以避免要付出較多研發(fā)經(jīng)費和較長投放市場周期的代價。隨著電子設(shè)

2、計自動化（EDA）技術(shù)的進展，基于可編程FPGA器件進行系統(tǒng)芯片集成的新設(shè)計方法，也正在快速地到代基于PCB板的傳統(tǒng)設(shè)計方式。因此，基于FPGA和VHDL語言實現(xiàn)在8*8點陣上的漢字靜態(tài)或一屏顯示問題。二、課題要求（1）技術(shù)要求1根據(jù)電路特點，用層次設(shè)計概念。將此設(shè)計任務(wù)分成若干模塊，規(guī)定每一模塊的功能和各模塊之間的借口，透視加深層次化設(shè)計概念；2軟件的原件管理深層含義，以及模塊元件之間的連接概念，對于不同目錄下的同一設(shè)計，如何熔合；3適配劃分前后的仿真內(nèi)容有何不同概念，仿真信號對象有何不同，有更深一步了解。熟悉了FPGA設(shè)計的調(diào)試過程中手段的多樣化；4按適配劃分后的管腳定位，同相關(guān)功能塊硬件

3、電路接口連線；（2）功能要求1在8*8點陣上顯示漢字2可以靜態(tài)顯示或一屏顯示3利用撥碼開關(guān)來實現(xiàn)靜態(tài)顯示與一屏顯示切換（3）本人的工作三、設(shè)計方案（1）工作原理 8*8點陣原理：按照要求可知，點陣模塊，共由8*8=64個發(fā)光二極管組成，如何在該點陣模塊上顯示漢字是本實驗的關(guān)鍵。先將要顯示的每幅圖像畫在8*8共64個小方格的矩形框中，再在有筆劃下落處的小方格里填上“1”，五筆劃處填上“0”，這樣就形成了與這個漢字所對應(yīng)的二進制數(shù)據(jù)在該矩形礦上的分布以“正”為例，點陣分布為：10000000100000011111000110000001111111111000100110001001100000

4、00（2）原理框圖四、單元電路設(shè)計，仿真結(jié)果與分析（1）靜態(tài)顯示“正”library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_Unsigned.all;use ieee.std_logic_ARITH.all;ENTITY peng isport(clk,en:in std_logic; lie:out std_logic_vector(7 downto 0); -列 com:out std_logic_vector(7 downto 0);-行End peng;Architecture a of peng issignal st

5、1:std_logic_vector(7 downto 0);signal osc:std_logic;signal osd:std_logic;signal d_ff:std_logic_vector(27 downto 0);signal data:std_logic_vector(7 downto 0);signal d0,d1,d2,d3,d4,d5,d6,d7:std_logic_vector(7 downto 0);signal lie0,lie1,lie2,lie3,lie4,lie5,lie6,lie7:std_logic_vector(7 downto 0);Begincom

6、<=data;lie<=st1;d0<="10000000"d1<="10000001"d2<="11110001"d3<="10000001"d4<="11111111"d5<="10001001"d6<="10001001"d7<="10000000"-字庫 正First:processbeginwait until clk='1'if(d_ff(27 do

7、wnto 0)>=2e8)then d_ff(27 downto 0)<="0000000000000000000000000000"else d_ff(27 downto 0)<=d_ff+1;end if;osc<=not d_ff(10);end process first;second:process(osc)begin if(osc='1' and osc'event and en='0')then if st1(7 downto 0)="00000000"or st1(7 dow

8、nto 0)="01111111"then st1(7 downto 0)<="11111110"data<=d0; elsif st1(7 downto 0)="11111110"then st1(7 downto 0)<="11111101"data<=d1; elsif st1(7 downto 0)="11111101"then st1(7 downto 0)<="11111011"data<=d2; elsif st1(7 dow

9、nto 0)="11111011"then st1(7 downto 0)<="11110111"data<=d3; elsif st1(7 downto 0)="11110111"then st1(7 downto 0)<="11101111"data<=d4; elsif st1(7 downto 0)="11101111"then st1(7 downto 0)<="11011111"data<=d5; elsif st1(7 dow

10、nto 0)="11011111"then st1(7 downto 0)<="10111111"data<=d6; elsif st1(7 downto 0)="10111111"then st1(7 downto 0)<="01111111"data<=d7; end if;end if;end process second;end a;（2）一屏顯示“上下五千年”Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_un

11、signed.all;Use ieee.std_logic_arith.all;Entity weng isPort( Clk,en:in std_logic; lie:out std_logic_vector(7 downto 0);-列 Com:out std_logic_vector(7 downto 0);-行End weng;Architecture a of weng issignal st1:std_logic_vector(7 downto 0);signal osc:std_logic;signal osd:std_logic;signal d_ff:std_logic_ve

12、ctor(27 downto 0);signal data:std_logic_vector(7 downto 0);signal d0,d1,d2,d3,d4,d5,d6,d7:std_logic_vector(7 downto 0);signal lie0,lie1,lie2,lie3,lie4,lie5,lie6,lie7:std_logic_vector(6 downto 0);begincom<=data;lie<=st1;D0<="10000000"when lie0(6 downto 0)="0000000"else&qu

13、ot;00000001"when lie0(6 downto 0)="0000001"else"10000000"when lie0(6 downto 0)="0000010"else"00010000"when lie0(6 downto 0)="0000011"else"00100100"when lie0(6 downto 0)="0000100"else"00000000"D1<="10000000&q

14、uot;when lie0(6 downto 0)="0000000"else"00000001"when lie0(6 downto 0)="0000001"else"10001001"when lie0(6 downto 0)="0000010"else"00010100"when lie0(6 downto 0)="0000011"else"00111011"when lie0(6 downto 0)="0000100&

15、quot;else"00000000"D2<="10000000"when lie0(6 downto 0)="0000000"else"00000001"when lie0(6 downto 0)="0000001"else"10001001"when lie0(6 downto 0)="0000010"else"00010100"when lie0(6 downto 0)="0000011"else&quo

16、t;00101010"when lie0(6 downto 0)="0000100"else"00000000"D3<="11111111"when lie0(6 downto 0)="0000000"else"11111111"when lie0(6 downto 0)="0000001"else"11111111"when lie0(6 downto 0)="0000010"else"11111100&qu

17、ot;when lie0(6 downto 0)="0000011"else"00101010"when lie0(6 downto 0)="0000100"else"00000000"D4<="10010000"when lie0(6 downto 0)="0000000"else"00001001"when lie0(6 downto 0)="0000001"else"10001001"when lie0(

18、6 downto 0)="0000010"else"00010010"when lie0(6 downto 0)="0000011"else"11111110"when lie0(6 downto 0)="0000100"else"00000000"D5<="10010000"when lie0(6 downto 0)="0000000"else"00010001"when lie0(6 downto 0)=&

19、quot;0000001"else"10001001"when lie0(6 downto 0)="0000010"else"00010001"when lie0(6 downto 0)="0000011"else"00101010"when lie0(6 downto 0)="0000100"else"00000000"D6<="10010000"when lie0(6 downto 0)="0000000&

20、quot;else"00100001"when lie0(6 downto 0)="0000001"else"11111000"when lie0(6 downto 0)="0000010"else"00010000"when lie0(6 downto 0)="0000011"else"00101010"when lie0(6 downto 0)="0000100"else"00000000"D7<=&quo

21、t;10000000"when lie0(6 downto 0)="0000000"else"00000001"when lie0(6 downto 0)="0000001"else"10000000"when lie0(6 downto 0)="0000010"else"00010000"when lie0(6 downto 0)="0000011"else"00100000"when lie0(6 downto 0)=&q

22、uot;0000100"else"00000000"first:processbeginwait until clk='1'if(d_ff(27 downto 0)>=2e8)thend_ff(27 downto 0)<="0000000000000000000000000000"elsed_ff(27 downto 0)<=d_ff+1;end if;osc<=not d_ff(10);osd<=not d_ff(26);end process first;second:process(osc)b

23、eginif(osc='1' and osc'event and en='0')then if st1(7 downto 0)="00000000"or st1(7 downto 0)="01111111"then st1(7 downto 0)<="11111110"data<=d0; elsif st1(7 downto 0)="11111110"then st1(7 downto 0)<="11111101"data<=d1;

24、 elsif st1(7 downto 0)="11111101"then st1(7 downto 0)<="11111011"data<=d2; elsif st1(7 downto 0)="11111011"then st1(7 downto 0)<="11110111"data<=d3; elsif st1(7 downto 0)="11110111"then st1(7 downto 0)<="11101111"data<=d4;

25、 elsif st1(7 downto 0)="11101111"then st1(7 downto 0)<="11011111"data<=d5; elsif st1(7 downto 0)="11011111"then st1(7 downto 0)<="10111111"data<=d6; elsif st1(7 downto 0)="10111111"then st1(7 downto 0)<="01111111"data<=d7;

26、 end if;end if;end process second;third:process(osd)beginif(osd='1' and osd'event and en='0')thenif lie0(6 downto 0)="0000100"then lie0(6 downto 0)<="0000000"else lie0(6 downto 0)<=lie0+1;end if;end if;end process third;end a;五頂層文件電路設(shè)計，仿真結(jié)果與分析頂層文件library

27、 ieee;use ieee.std_logic_1164.all;use ieee.std_logic_Unsigned.all;use ieee.std_logic_ARITH.all;entity zong is port( a:in std_logic_vector(1 downto 0); clk:in std_logic; hang:out std_logic_vector(7 downto 0); lie:out std_logic_vector(7 downto 0);end entity zong;architecture one of zong iscomponent pe

28、ng isport(clk,en:in std_logic; lie:out std_logic_vector(7 downto 0); -列 com:out std_logic_vector(7 downto 0);end component;component weng isPort( Clk,en:in std_logic; lie:out std_logic_vector(7 downto 0);-列 Com:out std_logic_vector(7 downto 0);-行end component;signal h1,h2:std_logic_vector(7 downto 0

29、);signal l1,l2:std_logic_vector(7 downto 0);beginu1:peng port map(clk=>clk,en=>a(1),com=>h1,lie=>l1);u2:weng port map(clk=>clk,en=>a(0),com=>h2,lie=>l2);hang<=h1 or h2;lie<=l1 or l2;end architecture one;六、調(diào)試結(jié)果創(chuàng)建工程在Quartus II 中新建一個VHDL File文件，將vhdl代碼輸入這個文件，并保存到工作目錄，名為zong.vhd。利用new preject wizard 工具創(chuàng)建一個工程，工程名為zong,頂層文件實體名為zong，并將上面創(chuàng)建的zong.vhd文件加入到工程中。編譯前設(shè)置（1）選擇目標芯片。用assignmemts-àsettings命令，彈出settings對話框，選擇目標芯片為EP2C5T