HV Process and Device高壓工藝與器件

HVProcessandDevice TD HV Agenda HighvoltageproductapplicationHVTechnologyintroductionHVvoltagestandarddevice0 5um5V 40VMixed signalTechnologyFeatures0 5um5V 40VMixed signalDesignFlexibility0 5umHVMixed SignalProcessFlow ModulesIssueindevelopment Highvoltageproductapplication HVTechnologyintroduction E V dE1 E2 E3 PNjunction HVTechnologyintroduction JunctionTerminationTechnologyFieldplate MFP MetalfieldplateandRFP resistivefieldplate FieldlimitingRing FLRRESURF ReducedSURfaceField Drain HNW N N Psub Source Gate FOX HPW N P HighvoltageStandardDevice DDDStructureHVMOS for8 12v Note NDDformationthroughNplustwiceimplant onlyforbigdimensionprocess HighvoltageStandardDevice DDD OffsetHVMOS for12 20v Note WithadditionallayerNDDafterpoly HighvoltageStandardDevice LDMOSHighCurrentoutput Lowdissipationoutput CDMOStechnologyiscreatedbymergingLDMOStechnologyandCMOStechnology ThemajorityofCDMOSprocessesareusedfordriverandpowerICs AddingBJToptions CDMOSwillbecomeBCDprocess CMOSHighdensitydigitalandanalog CDMOSHighdensitydigitalandanalog HighCurrentoutput Lowdissipationoutput HighvoltageStandardDevice Above30v LDMOS lateraldoublediffusionMOS 40 25V Vds Vgs devicestructure Criticaldimension A ChannellengthAaffectthebreakdownofpunchthroughandRdsonB DriftextensionTOB BV MajorC TOtoTOspaceC BV MajorD M1overlapdrainsideTOD BV MinorE PolyoverlapFOXE BV MinorDrainwelltoguardringProvidethefieldisolationandreducethelatchup 0 5um5V 40VMixed signalTechnologyFeatures 0 5um5V 40VMixed signalDesignFlexibility 0 5umHVMixed SignalProcessFlow Modules Ifonlynormal HVN Dep NMOS LowVtPMOS Dep PMOS 0 5umHVMixed SignalProcessFlow Modules PCM Pad Al3 Via2 Al2 Via1 Al1 P Plug Contact LowTCPoly2Res ONO HighRes LowTCRes Poly2 N PSD Spacer N PLDD Poly1 HighPolyRes PIPCAP ONO iscriticallayer Issueindevelopment HVNMOSSub thresholdleakage Sub thresholdleakinHVNMOSVTcurvecomparedto5vnormalNMOSdevice Andfromthegraph thisdevicemusthasaparasiticalNMOSparalleltoHVNMOS theparasiticalNMOSVTishigherorsmallerthanHVNMOS Issueindevelopment Drain Source Gate A NormalHVNMOSdeviceB C Parasiticaldevice Testcondition Vd 0 1v Vsub Vs 0v Vgsw