1操作系統(tǒng)精髓與設(shè)計(jì)原理英漢對(duì)照6thppt課件

1、Chapter 1Computer System OverviewDave BremerOtago Polytechnic, N.Z.2019, Prentice HallOperating Systems:Internals and Design Principles, 6/EWilliam StallingsRoadmap路標(biāo)Basic Elements基本構(gòu)成Processor Registers處理器寄存器Instruction Execution指令的執(zhí)行Interrupts中斷The Memory Hierarchy存儲(chǔ)器的層次Cache Memory高速緩存I/O Communi

2、cation TechniquesI/O通訊技術(shù)Operating System操作系統(tǒng) Exploits the hardware resources of one or more processors利用硬件資源的一個(gè)或多個(gè)處理器 Provides a set of services to system users為用戶提供一組服務(wù) Manages secondary memory and I/O devices管理輔助存儲(chǔ)器和I/O設(shè)備A Computers Basic Elements電腦的基本構(gòu)成 Processor處理器 Main Memory內(nèi)存 I/O Modules輸入輸出模

3、塊 System Bus系統(tǒng)總線Processor處理器 Controls operation, performs data processing控制操作，執(zhí)行數(shù)據(jù)處理 Two internal registers兩個(gè)內(nèi)部寄存器 Memory address resister (MAR)地址寄存器 Memory buffer register (MBR)緩沖寄存器 I/O address registerI/O地址寄存器 I/O buffer registerI/O緩沖寄存器Main Memory內(nèi)存 Volatile易失的 Data is typically lost when power

4、is removed Referred to as real memory or primary memory被稱(chēng)作實(shí)存儲(chǔ)器或主存儲(chǔ)器 Consists of a set of locations defined by sequentially numbers addresses由一組單元組成，這些單元由順序編號(hào)的地址定義 Containing either data or instructions存放數(shù)據(jù)或指令I(lǐng)/O ModulesI/O模塊 Moves data between the computer and the external environment such as: Stora

5、ge (e.g. hard drive)存儲(chǔ)器例如硬盤(pán)） Communications equipment通信設(shè)備 Terminals終端 Specified by an I/O Address Register由I/O地址寄存器確定 (I/OAR)（I/O地址寄存器）System Bus Communication among processors, main memory, and I/O modules在處理器內(nèi)存和I/O模塊間通訊Top-Level View頂層視圖P7）Roadmap Basic Elements Processor Registers Instruction Exe

6、cution Interrupts The Memory Hierarchy Cache Memory I/O Communication TechniquesProcessor Registers Faster and smaller than main memory比內(nèi)存快、小 User-visible registers用戶可見(jiàn)寄存器 Enable programmer to minimize main memory references by optimizing register use通過(guò)優(yōu)先使用寄存器減少內(nèi)存訪問(wèn) Control and status registers控制和狀態(tài)

7、寄存器 Used by processor to control operating of the processor用以控制處理器的操作 Used by privileged OS routines to control the execution of programs由特權(quán)操作系統(tǒng)例程使用以控制程序執(zhí)行User-Visible Registers用戶可見(jiàn)寄存器 May be referenced by machine language可以通過(guò)機(jī)器語(yǔ)言引用 Available to all programs application programs and system programs對(duì)

8、所有程序可用包括應(yīng)用程序和系統(tǒng)程序） Types of registers typically available are:通?？捎玫募拇嫫黝?lèi)型有： data, address, condition code registers.條件碼寄存器Data and Address Registers數(shù)據(jù)和地址寄存器 Data Often general purpose常常通用 But some restrictions may apply有時(shí)會(huì)有限制 Address Index Register變址寄存器 Segment pointer堆指針 Stack pointer棧指針Control and

9、Status Registers控制和狀態(tài)寄存器 Program counter (PC)程序計(jì)數(shù)器 Contains the address of an instruction to be fetched包含將取指令的地址 Instruction register (IR)指令寄存器 Contains the instruction most recently fetched包含最近取用的指令 Program status word (PSW)程序狀態(tài)字 Contains status information包含狀態(tài)信息Condition codes條件碼 Usually part of t

10、he control register通?？刂萍拇嫫鞯囊徊糠?Also called flags也稱(chēng)為標(biāo)記 Bits set by processor hardware as a result of operations處理器硬件為操作結(jié)果設(shè)置的位 Read only, intended for feedback regarding the results of instruction execution.只讀，用于反饋指令執(zhí)行結(jié)果Roadmap Basic Elements Processor Registers Instruction Execution Interrupts The Me

11、mory Hierarchy Cache Memory I/O Communication TechniquesInstruction Execution指令的執(zhí)行 A program consists of a set of instructions stored in memory處理器執(zhí)行的程序由一組存儲(chǔ)在內(nèi)存中的指令組成 Two steps兩個(gè)步驟 Processor reads (fetches) instructions from memory處理器從內(nèi)存中讀取指令 Processor executes each instruction處理器執(zhí)行每一條指令Basic Instruc

12、tion Cycle基本指令周期Instruction Fetch and Execute取指令和執(zhí)行指令 The processor fetches the instruction from memory處理器從內(nèi)存中讀取指令 Program counter (PC) holds address of the instruction to be fetched next程序計(jì)數(shù)器保存下一條將取指令的地址 PC is incremented after each fetch每次取指令后程序計(jì)數(shù)器自增Instruction Register指令寄存器 Fetched instruction is

13、 loaded into instruction register取到的指令載入到指令寄存器 Categories操作分類(lèi) Processor-memory, 處理器-存儲(chǔ)器 processor-I/O, 處理器-I/O Data processing, 數(shù)據(jù)處理 Control控制Characteristics of a Hypothetical Machine理想機(jī)器的特征Example of Program Execution程序執(zhí)行的例子Roadmap Basic Elements Processor Registers Instruction Execution Interrupts

14、 The Memory Hierarchy Cache Memory I/O Communication TechniquesInterrupts中斷 Interrupt the normal sequencing of the processor中斷處理器正常序列 Provided to improve processor utilization用于提高處理器效率 Most I/O devices are slower than the processor Processor must pause to wait for deviceCommon Classes of Interrupts中

15、斷的通常等級(jí)Flow of Control without Interrupts無(wú)中斷控制流程Interrupts and theInstruction Cycle終端和指令周期Transfer of Control via Interrupts通過(guò)中斷的控制轉(zhuǎn)移Instruction Cycle with Interrupts有中斷的指令周期Short I/O Wait短I/O等待Long I/O wait長(zhǎng)I/O等待Simple Interrupt Processing簡(jiǎn)單的中斷處理Changes in Memory and Registers for an Interrupt內(nèi)存和寄存器

16、因中斷而產(chǎn)生的變化Multiple Interrupts多中斷 Suppose an interrupt occurs while another interrupt is being processed.假設(shè)當(dāng)一個(gè)中斷正在處理，另一個(gè)中斷出現(xiàn) E.g. printing data being received via communications line. Two approaches:兩個(gè)方法 Disable interrupts during interrupt processing在一個(gè)中斷處理中禁止其他中斷 Use a priority scheme.使用優(yōu)先級(jí)Sequential

17、 Interrupt Processing順序中斷處理Nested Interrupt Processing嵌套中斷處理Example of Nested Interrupts嵌套中斷的例子Multiprogramming多道程序設(shè)計(jì) Processor has more than one program to execute處理器有多個(gè)程序要執(zhí)行 The sequence the programs are executed depend on their relative priority and whether they are waiting for I/O程序的執(zhí)行順序取決于他們的相對(duì)

18、優(yōu)先級(jí)以及是否正在等待I/O After an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt一個(gè)中斷處理完成后，控制權(quán)可能不會(huì)立刻返回到中斷時(shí)執(zhí)行到的程序而可能轉(zhuǎn)移到其他待運(yùn)行的具有更高優(yōu)先級(jí)的其他程序）Roadmap Basic Elements Processor Registers Instruction Execution Interrupts The Memory Hierarchy Cache Mem

19、ory I/O Communication TechniquesMemory Hierarchy存儲(chǔ)器層次 Major constraints in memory存儲(chǔ)器的主要局限 Amount容量 Speed速度 Expense費(fèi)用 Faster access time, greater cost per bit存取時(shí)間越短，每位價(jià)格越高 Greater capacity, smaller cost per bit容量越大，每位價(jià)格越低 Greater capacity, slower access speed容量越大，存取速度越小The Memory Hierarchy Going down

20、 the hierarchy沿著結(jié)構(gòu)向下 Decreasing cost per bit每位價(jià)格遞減 Increasing capacity容量遞增 Increasing access time存取時(shí)間遞增 Decreasing frequency of access to the memory by the processor存儲(chǔ)器訪問(wèn)頻度遞減Secondary Memory二級(jí)存儲(chǔ)器 Auxiliary memory亦輔助存儲(chǔ)器 External外部的 Nonvolatile非易失的 Used to store program and data files用于存儲(chǔ)程序和數(shù)據(jù)文件Roadma

21、p Basic Elements Processor Registers Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication TechniquesCache Memory高速緩存 Invisible to the OS對(duì)于操作系統(tǒng)不可見(jiàn) Interacts with other memory management hardware與其他存儲(chǔ)器管理硬件互動(dòng) Processor must access memory at least once per instruction cyc

22、le每個(gè)指令周期處理器至少訪問(wèn)一次內(nèi)存 Processor speed faster than memory access speed處理器速度遠(yuǎn)快于內(nèi)存訪問(wèn)速度 Exploit the principle of locality with a small fast memory利用局部性原理在處理器和內(nèi)存間提供一個(gè)容量小速度快的存儲(chǔ)器Principal of Locality局部性原理 More details later but in short 之后更多細(xì)節(jié)但簡(jiǎn)而言之 Data which is required soon is often close to the current da

23、ta最近調(diào)用的數(shù)據(jù)常常和當(dāng)前數(shù)據(jù)比較近 If data is referenced, then its neighbour might be needed soon.如果數(shù)據(jù)被調(diào)用了，那么他的鄰居可能很快就會(huì)被需要了Cache and Main Memory高速緩存和主存Cache Principles Contains copy of a portion of main memory包含部分主存數(shù)據(jù)的副本 Processor first checks cache處理器首先檢查高速緩存 If not found, block of memory read into cache如果沒(méi)有找到，（有

24、固定字節(jié)數(shù)的一塊內(nèi)存讀取到緩存 Because of locality of reference, likely future memory references are in that block由于局部性訪問(wèn)，緊接著的內(nèi)存訪問(wèn)很可能都在這個(gè)內(nèi)存塊中Cache/Main-Memory Structure高速緩存/內(nèi)存結(jié)構(gòu)Cache Read Operation高速緩存讀操作Cache Design Issues高速緩存設(shè)計(jì)問(wèn)題 Main categories are:主要分類(lèi)有 Cache size高速緩存大小 Block size塊大小 Mapping function映射函數(shù) Repla

25、cement algorithm替換算法 Write policy寫(xiě)策略Size issues尺寸問(wèn)題 Cache size高速緩存大小 Small caches have significant impact on performance適當(dāng)小的高速緩存對(duì)性能有顯著影響 Block size塊大小 The unit of data exchanged between cache and main memory即高速緩存和主存間數(shù)據(jù)交換的單位 Larger block size means more hits塊越大，命中率越高 But too large reduces chance of r

26、euse.但太大會(huì)降低重用率Mapping function映射函數(shù) Determines which cache location the block will occupy確定這個(gè)塊將占用高速緩存哪個(gè)位置 Two constraints:兩個(gè)約束條件： When one block read in, another may need replaced當(dāng)一個(gè)塊讀入高速緩存時(shí)，另一個(gè)將會(huì)被替代出高速緩存） Complexity of mapping function increases circuitry costs for searching.映射函數(shù)越靈活，搜索以確定某塊是否在高速緩存中）

27、（邏輯電路越復(fù)雜Replacement Algorithm替換算法 Chooses which block to replace when a new block is to be loaded into the cache.當(dāng)要把一個(gè)新塊載入cache時(shí)，選擇要替換哪個(gè)塊 Ideally replacing a block that isnt likely to be needed again理想上替換掉一個(gè)不會(huì)再使用的塊 Impossible to guarantee無(wú)法保證 Effective strategy is to replace a block that has been us

28、ed less than others高效的策略要求替換使用最少的塊 Least Recently Used (LRU)最近最少使用Write policy寫(xiě)策略 Dictates when the memory write operation takes place規(guī)定何時(shí)發(fā)生寫(xiě)操作 Can occur every time the block is updated每當(dāng)塊更新時(shí)都有可能發(fā)生寫(xiě)操作） Can occur when the block is replaced只要塊替換時(shí)有可能發(fā)生寫(xiě)操作） Minimize write operations減少內(nèi)存寫(xiě)操作 Leave main me

29、mory in an obsolete state使主存處于一種廢棄的狀態(tài)Roadmap Basic Elements Processor Registers Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication TechniquesI/O TechniquesI/O通信技術(shù) When the processor encounters an instruction relating to I/O,當(dāng)處理器遇到一個(gè)與I/O相關(guān)的指令時(shí) it executes that instru

30、ction by issuing a command to the appropriate I/O module.通過(guò)給適當(dāng)?shù)腎/O模塊發(fā)出命令來(lái)執(zhí)行這個(gè)指令 Three techniques are possible for I/O operations:對(duì)I/O操作可能有三種技術(shù)： Programmed I/O可編程I/O Interrupt-driven I/O中斷驅(qū)動(dòng)I/O Direct memory access (DMA)直接內(nèi)存存取Programmed I/O The I/O module performs the requested action 這個(gè)I/O模塊執(zhí)行請(qǐng)求動(dòng)作 t

31、hen sets the appropriate bits in the I/O status register進(jìn)而設(shè)置相應(yīng)位的I/O狀態(tài)寄存器 but takes no further action to alert the processor.但并不進(jìn)一步提醒處理器 As there are no interrupts, the processor must determine when the instruction is complete因?yàn)闆](méi)有中斷，處理器必須決定指令何時(shí)完成Programmed I/OInstruction Set指令集 Control控制 Used to activate and instruct device用于激活和指示設(shè)備 Status狀態(tài) Tests status conditions測(cè)試I/O及外圍設(shè)備狀態(tài)條件 Transfer傳送 Read/write between process register and device在處理器寄存器和外設(shè)間讀寫(xiě)數(shù)據(jù)Programmed I/O Example Data read in a word at