數(shù)字邏輯課后答案第五章

1、第五章 習(xí)題答案1. 畫出與陣列編程點解: 2. 畫出或陣列編程點解: 3. 與、或陣列均可編程,畫出編程點。解 ;-X 1X 2X 3X 44. 4變量 LUT 編程解:5. 用 VHDL 寫出 4輸入與門解: 源代碼:LIBRARY IEEE ;USE IEEE . STD_LOGIC_1164. ALL ;ENTITY and4 ISPORT (a, b , c , d :IN STD_LOGIC;x :OUT STD_LOGIC ;END and4;ARCHITECTURE and4_arc OF and4 ISBEGINx <=a AND b AND c AND d;END a

2、nd4_arc;6. 用 VHDL 寫出 4輸入或門解: 源代碼:LIBRARY IEEE ;USE IEEE . STD_LOGIC_1164. ALL ; 1A-BB -F 32A 0A 1A 2A 3 SOP 輸出ENTITY or4 ISPORT (a, b , c , d :IN STD_LOGIC;x :OUT STD_LOGIC ;END or4;ARCHITECTURE or4_arc OF or4 ISBEGINx <=a OR b OR c OR d;END or4_arc;7. 用 VHDL 寫出 SOP 表達(dá)式解:源代碼:LIBRARY IEEE ;USE IEE

3、E . STD_LOGIC_1164. ALL ;ENTITY sop ISPORT (a, b , c , d , e , f :IN STD_LOGIC;x :OUT STD_LOGIC ;END sop ;ARCHITECTURE sop_arc OF sop ISBEGINx <=(a AND b OR (c AND d OR (e AND f;END sop_arc;8. 用 VHDL 寫出布爾表達(dá)式解:源代碼:LIBRARY IEEE ;USE IEEE . STD_LOGIC_1164. ALL ;ENTITY boolean ISPORT (a, b , c :IN ST

4、D_LOGIC;f :OUT STD_LOGIC ;END boolean ;ARCHITECTURE boolean_arc OF boolean ISBEGINf <=(a OR (NOT b OR c AND (a OR b OR (NOT c AND (NOT a OR (NOT b OR (NOT c;END boolean_arc;9. 用 VHDL 結(jié)構(gòu)法寫出 SOP 表達(dá)式解:源代碼:三輸入與非門的邏輯描述LIBRARY IEEE ;USE IEEE . STD_LOGIC_1164. ALL ;ENTITY nand3 ISPORT (a, b , c :IN STD_

5、LOGIC;x :OUT STD_LOGIC ;END nand3;ARCHITECTURE nand3_arc OF nand3 ISBEGINx <=NOT (a AND b AND c;END nand3_arc;頂層結(jié)構(gòu)描述文件LIBRARY IEEE ;USE IEEE . STD_LOGIC_1164. ALL ;ENTITY sop ISPORT (in1, in2, in3, in4, in5, in6, in7, in8, in9:IN STD_LOGIC; out4:OUT STD_LOGIC;END sop ;ARCHITECTURE sop_arc OF sop

6、ISCOMPONENT nand3PORT (a, b , c :IN STD_LOGIC;x :OUT STD_LOGIC ;END COMPONENT;SIGNAL out1, out2, out3:STD_LOGIC;BEGINu1:nand3 PORT MAP (in1, in2, in3, out1 ;u2:nand3 PORT MAP (in4, in5, in6, out2 ;u3:nand3 PORT MAP (in7, in8, in9, out3 ;u4:nand3 PORT MAP (out1, out2, out3, out4 ;END sop;10. 用 VHDL 數(shù)

7、據(jù)流法寫出 SOP 表達(dá)式解:源代碼:LIBRARY IEEE ;USE IEEE . STD_LOGIC_1164. ALL ;ENTITY sop ISPORT (in1, in2, in3, in4, in5, in6, in7, in8, in9:IN STD_LOGIC; out4:OUT STD_LOGIC;END sop ;ARCHITECTURE sop_arc OF sop ISBEGINout4<=(in1 AND in2 AND in3 OR (in4 AND in5 AND in6 OR (in7 AND in8 AND in9;END sop_arc;13. 用

8、 VHDL 設(shè)計 3-8譯碼器解:源代碼:LIBRARY IEEE ;USE IEEE . STD_LOGIC_1164. ALL ;ENTITY decoder_3_to_8 ISPORT (a , b , c , g1, g2a , g2b :IN STD_LOGIC;y :OUT STD_LOGIC _VECTOR(7 downto 0 ; END decoder_3_to_8;ARCHITECTURE rt1 OF decoder_3_to_8 ISSIGNAL indata :STD_LOGIC _VECTOR(2 downto 0 ;BEGINindata <=c &

9、 b & a;PROCESS (indata , g1, g2a , g2b BEGINIF (g1=1 AND g2a=0 AND g2b=0 THENCASE indata ISWHEN "000"=>y <="11111110" ;WHEN "001"=>y <="11111101" ;WHEN "010"=>y <="11111011" ;WHEN "011"=>y <="11110

10、111" ;WHEN "100"=>y <="11101111" ;WHEN "101"=>y <="11011111" ;WHEN "110"=>y <="10111111" ;WHEN others =>y <="01111111" ;END CASE;ELSEy <="11111111" ;END IF;END PROCESS ;END rt1;14. 用 VHDL

11、設(shè)計七段顯示譯碼器解:源代碼:LIBRARY IEEE ;USE IEEE . STD_LOGIC_1164. ALL ;ENTITY segment7 ISPORT (xin :IN STD_LOGIC _VECTOR(3 downto 0 ;lt , rbi :IN STD_LOGIC;yout :OUT STD_LOGIC _VECTOR(6 downto 0 ;birbo :INOUT STD_LOGIC ;END segment7;ARCHITECTURE seg7448 OF segment7 ISSIGNAL sig_xin:STD_LOGIC _VECTOR(3 downto

12、0 ; BEGINsig_xin<=xin ;PROCESS (sig_xin, lt , rbi , birbo BEGINIF (birbo =0 THENyout <="0000000" ;ELSIF (lt =0 THENyout <="1111111" ;birbo <=1 ;ELSIF (rbi =0 AND sig_xin="0000" THEN yout <="0000000" ;birbo <=0 ;ELSIF (rbi =1 AND sig_xin="

13、;0000" THEN yout <="1111110" ;birbo <=1 ;ELSEbirbo <=1 ;CASE sig_xin ISWHEN "0001"=>yout <="0110000" ; WHEN "0010"=>yout <="1101101" ; WHEN "0011"=>yout <="1111001" ; WHEN "0100"=>yout

14、<="0110011" ; WHEN "0101"=>yout <="1011011" ; WHEN "0110"=>yout <="0011111" ; WHEN "0111"=>yout <="1110000" ; WHEN "1000"=>yout <="1111111" ; WHEN "1001"=>yout <="

15、;1110011" ; WHEN others =>yout <="0100011" ; END CASE;END IF;END PROCESS ;END seg7448;15. 用 VHDL 設(shè)計 8/3優(yōu)先編碼器解:源代碼:LIBRARY IEEE ;USE IEEE . STD_LOGIC_1164. ALL ;ENTITY priorityencoder ISPORT (din :IN STD_LOGIC _VECTOR(7 downto 0 ;ei :IN STD_LOGIC;yout :OUT STD_LOGIC _VECTOR(2 dow

16、nto 0 ; eo , gs :OUT STD_LOGIC ;END priorityencoder ;ARCHITECTURE cod74148 OF priorityencoder ISBEGINPROCESS (ei , din BEGINIF (ei =1 THENyout <="111" ;eo <=1 ;gs <=1 ;ELSEIF (din(7=0 THENyout <="000" ;eo <=1 ;gs <=0 ;ELSIF (din(6=0 THENyout <="001"

17、 ;eo <=1 ;gs <=0 ;ELSIF (din(5=0 THENyout <="010" ;eo <=1 ;gs <=0 ;ELSIF (din(4=0 THENyout <="011" ;eo <=1 ;gs <=0 ;ELSIF (din(3=0 THENyout <="100" ;eo <=1 ;gs <=0 ;ELSIF (din(2=0 THENyout <="101" ;eo <=1 ;gs <=0 ;ELSI

18、F (din(1=0 THENyout <="110" ;eo <=1 ;gs <=0 ;ELSIF (din(0=0 THENyout <="111" ;eo <=1 ;gs <=0 ;ELSIF (din="11111111" THEN yout <="111" ;eo <=0 ;gs <=1 ;END IF;END IF;END PROCESS ;END cod74148;16. 用 VHDL 設(shè)計 BCD 碼至二進(jìn)制碼轉(zhuǎn)換器。解:源代碼:library

19、ieee;entity bcdtobi isport (bcdcode : IN STD_LOGIC_VECTOR(7 DOWNTO 0;start: in std_logic;qbit : OUT STD_LOGIC_VECTOR(3 DOWNTO 0;end;architecture behavioral of bcdtobi isbeginprocess(startbeginif start='0' thencase bcdcode(7 downto 0 iswhen "00000000"=>qbit(3 downto 0<="0

20、000" when "00000001"=>qbit(3 downto 0<="0001" when "00000010"=>qbit(3 downto 0<="0010" when "00000011"=>qbit(3 downto 0<="0011" when "00000100"=>qbit(3 downto 0<="0100" when "00000101&qu

21、ot;=>qbit(3 downto 0<="0101" when "00000110"=>qbit(3 downto 0<="0110" when "00000111"=>qbit(3 downto 0<="0111" when "00001000"=>qbit(3 downto 0<="1000" when "00001001"=>qbit(3 downto 0<=&quo

22、t;1001" when "00010000"=>qbit(3 downto 0<="1010" when "00010001"=>qbit(3 downto 0<="1011" when "00010010"=>qbit(3 downto 0<="1100"when "00010011"=>qbit(3 downto 0<="1101"when "00010100&q

23、uot;=>qbit(3 downto 0<="1110"when "00010101"=>qbit(3 downto 0<="1111"when others=>qbit(3 downto 0<="0000"end case;elseqbit(3 downto 0<="0000"end if;end process;end behavioral;17. 用 VHDL 設(shè)計 4位寄存器解:異步復(fù)位源代碼:LIBRARY IEEE ;USE IEEE .

24、STD_LOGIC_1164. ALL ;ENTITY register_4 ISPORT (clk , r :IN STD_LOGIC;din :IN STD_LOGIC _VECTOR(3 downto 0 ; qout :OUT STD_LOGIC _VECTOR(3 downto 0 ; END register_4;ARCHITECTURE rge_arc OF register_4 ISSIGNAL q_temp:STD_LOGIC _VECTOR(3 downto 0 ; BEGINPROCESS (clk , r BEGINIF (r =1 THENq_temp<=&qu

25、ot;0000" ;ELSIF (clkevent AND clk =1 THENq_temp<=din ;END IF;qout <=q_temp;END PROCESS ;END rge_arc;18. 用 VHDL 設(shè)計 4位雙向移位寄存器解:s1、 s0控制工作方式, dsl 為左移數(shù)據(jù)輸入, dsr 為右移數(shù)據(jù)輸入。 源代碼:LIBRARY IEEE ;USE IEEE . STD_LOGIC_1164. ALL ;ENTITY shiftreg ISPORT (clk , r , dsr , dsl :IN STD_LOGIC;s1, s0:IN STD_LO

26、GIC; -function selectdin :IN STD_LOGIC _VECTOR(3 downto 0 ; -data inqout :OUT STD_LOGIC _VECTOR(3 downto 0 ; -data out END shiftreg ;ARCHITECTURE ls74194 OF shiftreg ISSIGNAL iq :STD_LOGIC _VECTOR(3 downto 0 ;SIGNAL s :STD_LOGIC _VECTOR(1 downto 0 ;BEGINs <=s1 & s0;PROCESS (clk , r BEGINIF (r =0 THENiq <="0000" ;ELSIF (clkevent AND clk =1 THENCASE s ISWHEN "00"=>null ;WHEN "01"=>iq <=dsr & din(3 downto 1 ; -right WHEN "10"=>iq <=din (2 downto 0 &