北航電子電路設(shè)計(jì)數(shù)字部分實(shí)驗(yàn)報(bào)告.docx

電子電路設(shè)計(jì)數(shù)字部分實(shí)驗(yàn)報(bào)告學(xué) 院： 姓名：實(shí)驗(yàn)一 簡(jiǎn)單組合邏輯設(shè)計(jì)實(shí)驗(yàn)內(nèi)容描述一個(gè)可綜合的數(shù)據(jù)比較器，比較數(shù)據(jù)a 、b的大小，若相同，則給出結(jié)果1，否則給出結(jié)果0。實(shí)驗(yàn)仿真結(jié)果實(shí)驗(yàn)代碼主程序module compare(equal,a,b); input7:0 a,b; output equal; assign equal=(ab)?1:0; endmodule測(cè)試程序module t; reg7:0 a,b; reg clock,k; wire equal; initial begin a=0; b=0; clock=0; k=0; end always #50 clock = clock; always (posedge clock) begin a0=$random%2; a1=$random%2; a2=$random%2; a3=$random%2; a4=$random%2; a5=$random%2; a6=$random%2; a7=$random%2; b0=$random%2; b1=$random%2; b2=$random%2; b3=$random%2; b4=$random%2; b5=$random%2; b6=$random%2; b7=$random%2; end initial begin #100000 $stop;end compare m(.equal(equal),.a(a),.b(b); endmodule實(shí)驗(yàn)二 簡(jiǎn)單分頻時(shí)序邏輯電路的設(shè)計(jì)實(shí)驗(yàn)內(nèi)容用always塊和(posedge clk)或(negedge clk)的結(jié)構(gòu)表述一個(gè)1/2分頻器的可綜合模型，觀察時(shí)序仿真結(jié)果。實(shí)驗(yàn)仿真結(jié)果實(shí)驗(yàn)代碼主程序module half_clk(reset,clk_in,clk_out); input clk_in,reset; output clk_out; reg clk_out; always(negedge clk_in) begin if(!reset) clk_out=0; else clk_out=clk_out; end endmodule測(cè)試程序timescale 1ns/100psdefine clk_cycle 50module top; reg clk,reset; wire clk_out; always #clk_cycle clk=clk; initial begin clk=0; reset=1; #10 reset=0; #110 reset=1; #100000 $stop; end half_clk m0(.reset(reset),.clk_in(clk),.clk_out(clk_out);endmodule實(shí)驗(yàn)三 利用條件語(yǔ)句實(shí)現(xiàn)計(jì)數(shù)分頻時(shí)序電路實(shí)驗(yàn)內(nèi)容利用10MHz的時(shí)鐘，設(shè)計(jì)一個(gè)單周期形狀的周期波形。實(shí)驗(yàn)仿真結(jié)果實(shí)驗(yàn)代碼主程序module fdivision(RESET,F10M,out); input F10M,RESET; output out; reg out; reg7:0 i; always (posedge F10M) if(!RESET) begin out=0; i=0; end else if(i=2|i=3) begin out=out; i=i+1; end else if(i=5) i=1; else i=i+1; endmodule測(cè)試程序timescale 1ns/100psmodule division_top; reg F10M,RESET; wire out; always #50 F10M=F10M; initial begin RESET=1; F10M=0; #90 RESET=0; #100 RESET=1; #10000 $stop; end fdivision fdivision(.RESET(RESET),.F10M(F10M),.out(out);endmodule實(shí)驗(yàn)四 阻塞賦值與非阻塞賦值的區(qū)別實(shí)驗(yàn)內(nèi)容比較四種不同的寫(xiě)法，觀察阻塞與非阻塞賦值的區(qū)別。Blocking：always (posedge clk) begin b=a; c=b; endBlocking1：always (posedge clk) begin c=b;b=a;endBlocking2：always (posedge clk) b=a;always (posedge clk) c=b;non_Blocking：always(posedge clk) begin b=a; c=b; End實(shí)驗(yàn)仿真結(jié)果實(shí)驗(yàn)代碼主程序module blocking(clk,a,b,c); output3:0 b,c; input3:0 a; input clk; reg3:0 b,c; always (posedge clk) begin b=a; c=b; endendmodule測(cè)試部分timescale 1 ns/100 psinclude ./blocking.vinclude ./blocking1.vinclude ./blocking2.vinclude ./non_blocking.vmodule compareTop; wire3:0b11,c11,b12,c12,b13,c13,b2,c2; reg3:0a; reg clk; initial begin clk=0; forever#50 clk=clk; end initial begin a=4h3; $display(%d,a); #100 a=4h7; $display(%d,a); #100 a=4hf; $display(%d,a); #100 a=4ha; $display(%d,a); #100 a=4h2; $display(%d,a); #100 $stop; end blocking blocking(clk,a,b11,c11); blocking1 blocking1(clk,a,b12,c12); blocking2 blocking2(clk,a,b13,c13); non_blocking non_blocking(clk,a,b2,c2);endmodule實(shí)驗(yàn)五 用always塊實(shí)現(xiàn)較復(fù)雜的組合邏輯實(shí)驗(yàn)?zāi)康倪\(yùn)用always塊設(shè)計(jì)一個(gè)8路數(shù)據(jù)選擇器。要求：每路輸入數(shù)據(jù)與輸出數(shù)據(jù)均為4位2進(jìn)制數(shù)，當(dāng)選擇開(kāi)關(guān)（至少3位）或輸入數(shù)據(jù)發(fā)生變化時(shí)，輸出數(shù)據(jù)也相應(yīng)地變化。實(shí)驗(yàn)仿真結(jié)果實(shí)驗(yàn)代碼主程序module alu(out,opcode,a1,a2,a3,a4,a5,a6,a7,a8); output3:0 out; reg3:0 out; input3:0 a0,a1,a2,a3,a4,a5,a6,a7; input2:0 opcode; always(opcode or a1 or a2 or a3 or a4 or a5 or a6 or a7 or a0) begin case(opcode) 3d0: out=a0; 3d1: out=a1; 3d2: out=a2; 3d3: out=a3; 3d4: out=a4; 3d5: out=a5; 3d6: out=a6; 3d7: out=a7; default:out=4b0000; endcase endendmodule測(cè)試程序timescale 1ns/1nsinclude ./main5.vmodule alutext; wire3:0 out; reg3:0 a1,a2,a3,a4,a5,a6,a7,a8; reg2:0 opcode; initial begin a1=$random%16; a2=$random%16; a3=$random%16; a4=$random%16; a5=$random%16; a6=$random%16; a7=$random%16; a8=$random%16; repeat(100) begin #100 opcode=$random%8; a1=$random%16; a2=$random%16; a3=$random%16; a4=$random%16; a5=$random%16; a6=$random%16; a7=$random%16; a8=$random%16; end #100 $stop; end alu alu(out,opcode,a1,a2,a3,a4,a5,a6,a7,a8);endmodule 實(shí)驗(yàn)六 在 Verilog HDL中使用函數(shù)實(shí)驗(yàn)?zāi)康脑O(shè)計(jì)一個(gè)帶控制端的邏輯運(yùn)算電路，分別完成正整數(shù)的平方、立方和最大數(shù)為5的階乘運(yùn)算。實(shí)驗(yàn)仿真結(jié)果實(shí)驗(yàn)代碼主程序module tryfunct(clk,n,result1,result2,result3,reset); output31:0result1,result2,result3; input3:0n; input reset,clk; reg31:0result1,result2,result3; always(posedge clk) begin if(!reset) begin result1=0; result2=0; result3=0; end else begin result1=fun1(n); result2=fun2(n); result3=fun3(n); end end function31:0fun1; input3:0operand; fun1=operand*operand; endfunction function31:0fun2; input3:0operand; begin fun2=operand*operand; fun2=operand*fun2; end endfunction function31:0fun3; input3:0operand; reg3:0index; begin fun3=1; if(operand11) for(index=2;index=operand;index=index+1) fun3=index*fun3; else for(index=2;index=10;index=index+1) fun3=index*fun3; end endfunction endmodule測(cè)試程序include./main6.vtimescale 1ns/100psmodule tryfunctTop; reg3:0 n,i; reg reset,clk; wire31:0result1,result2,result3; initial begin clk=0; n=0; reset=1; #100 reset=0; #100 reset=1; for(i=0;iy) begin tmp=x; x=y; y=tmp; end endtaskendmodule測(cè)試部分1timescale 1ns/100psinclude main7.vmodule task_Top; reg7:0a,b,c,d; wire7:0ra,rb,rc,rd; initial begin a=0;b=0;c=0;d=0; repeat(50) begin #100 a=$random%255; b=$random%255; c=$random%255; d=$random%255; end #100 $stop; end rank rank(.ra(ra),.rb(rb),.rc(rc),.rd(rd),.a(a),.b(b),.c(c),.d(d); endmodule主程序2module rank(a,rst,clk,ra,rb,rc,rd); output7:0ra,rb,rc,rd; input7:0a; input clk,rst; reg7:0ra,rb,rc,rd; reg7:0va,vb,vc,vd; reg3:0i; always(posedge clk or negedge clk) begin if(!rst) begin va=0; vb=0; vc=0; vd=0; i=0; end else begin if(iy) begin tmp=x; x=y; y=tmp; end endtask endmodule測(cè)試部分2timescale 1ns/100psinclude main7_other.vmodule task_Top; reg7:0a; wire7:0ra,rb,rc,rd; reg clk,rst; initial begin a=0; rst=0; clk=0; #50 rst=1; #100 a=8$random; #100 a=8$random; #100 a=8$random; #100 a=8$random; #100 a=8$random; #100 a=8$random; #100 a=8$random; #100 a=8$random; #100 $stop; end always #100 clk=clk; rank rank(.a(a),.rst(rst),.clk(clk),.ra(ra),.rb(rb),.rc(rc),.rd(rd); endmodule實(shí)驗(yàn)八 利用有限狀態(tài)機(jī)進(jìn)行時(shí)序邏輯的設(shè)計(jì)實(shí)驗(yàn)?zāi)康脑O(shè)計(jì)一個(gè)串行數(shù)據(jù)檢測(cè)器。要求連續(xù)四個(gè)或四個(gè)以上為1 時(shí)輸出1，其他輸入情況下為0.實(shí)驗(yàn)仿真結(jié)果實(shí)驗(yàn)代碼主程序module seqdet(x,z,clk,rst,state); input x,clk,rst; output z; output2:0 state; reg2:0 state; wire z; parameter IDLE=d0,A=d1,B=d2,C=d3,D=d4; assign z=(state=D&x=1)?1:0; always(posedge clk) if(!rst) begin state=IDLE; end else casex(state) IDLE: if(x=1) begin state=A; end A: if(x=1) begin state=B; end else begin state=IDLE; end B: if(x=1) begin state=C; end else begin state=IDLE; end C: if(x=1) begin state=D; end else begin state=IDLE; end D: if(x=1) begin state=D; end else begin state=IDLE; end default:state=IDLE; endcase endmodule 測(cè)試代碼include main8.vmodule seqdet_Top; reg clk,rst; reg23:0 data; wire2:0 state; wire z,x; assign x=data23; always #10 clk=clk; always(posedge clk) data=data22:0,data23; initial begin clk=0; rst=1; #2 rst=0; #30 rst=1; data=b1001_1111_0111_1110; #500 $stop; end seqdet m(x,z,clk,rst,state);endmodule實(shí)驗(yàn)九 樓梯燈實(shí)驗(yàn)?zāi)康臉窍碌綐巧弦来斡?個(gè)感應(yīng)燈：燈1、燈2、燈3。當(dāng)行人上下樓梯時(shí)，各個(gè)燈感應(yīng)到后自動(dòng)點(diǎn)亮，若在8s內(nèi)感應(yīng)信號(hào)消失，則點(diǎn)亮8s，若感應(yīng)信號(hào)存在時(shí)間超過(guò)8s，則感應(yīng)信號(hào)消失4s后燈自動(dòng)關(guān)閉。任務(wù)1：做出如上邏輯電路設(shè)計(jì)并仿真；任務(wù)2：考慮去抖情況，對(duì)于感應(yīng)信號(hào)到達(dá)存在毛刺(小于0.5s)，設(shè)計(jì)合適邏輯并剔出。任務(wù)3：若為節(jié)約能源，下一個(gè)燈點(diǎn)亮的同時(shí)將自動(dòng)關(guān)閉上一個(gè)燈，做出如上邏輯設(shè)計(jì)并仿真（僅考慮一個(gè)人的情況）實(shí)驗(yàn)仿真結(jié)果實(shí)驗(yàn)代碼主程序module light_All(clk10,rst,switch,light); input clk10,rst; input2:0switch; output2:0light; reg2:0state1,state2,state3; reg7:0count1,count2,count3; reg2:0count_1,count_2,count_3; reg2:0light; parameter state1_start=3b000,state2_start=3b000,state3_start=3b000, state1_work=3b001,state2_work=3b001,state3_work=3b001, state1_up=3b010,state2_up=3b010,state3_up=3b010, state1_down=3b011,state2_down=3b011,state3_down=3b011, state1_other=3b100,state2_other=3b100,state3_other=3b100; always(posedge clk10) if(!rst) begin state1=state1_start; count1=8b0; count_1=3b0; end else if(switch0=b1&count_14) count_1=count_1+1; else case(state1) state1_start: if(switch0=b1) begin state1=state1_up; count1=78; end else begin state1=state1_start; light00) begin count1=count1-1; if(switch0=b0&(state2=3b010|state3=3b010) begin light0=b0; state1=state1_down; end end else if(switch0=b0) begin state1=state1_down; end else begin state1=state1_other; count1=39; end state1_other: if(switch0=b1) state10) begin count1=count1-1; if(switch0=b0&(state2=3b010|state3=3b010) begin light0=b0; state1=state1_down; end end else state1=state1_down; state1_down: begin light0=b0; count_1=3b0; state1=state1_start; end state1_up: begin light0=b1; state1=state1_work; end default: state1=state1_start; endcase always(posedge clk10) if(!rst) begin state2=state2_start; count2=8b0; count_2=3b0; end else if(switch1=b1&count_24) count_2=count_2+1; else case(state2) state2_start: if(switch1=b1) begin state2=state2_up; count2=78; end else begin state2=state2_start; light10) begin count2=count2-1; if(switch1=b0&(state1=3b010|state3=3b010) begin light1=b0; state2=state2_down; end end else if(switch1=b0) begin state2=state2_down; end else begin state2=state2_other; count2=39; end state2_other: if(switch1=b1) state20) begin count2=count2-1; if(switch1=b0&(state1=3b010|state3=3b010) begin light1=b0; state2=state2_down; end end else state2=state2_down; state2_down: begin light1=b0; count_2=3b0; state2=state2_start; end state2_up: begin light1=b1; state2=state2_work; end default: state2=state2_start; endcase always(posedge clk10) if(!rst) begin state3=state3_start; count3=8b0; count_3=3b0; end else if(switch2=b1&count_34) count_3=count_3+1; else case(state3) state3_start: if(switch2=b1) begin state3=state3_up; count3=78; end else begin state3=state3_start; light20) begin count3=count3-1; if(switch2=b0&(state1=3b010|state2=3b010) begin light2=b0; state3=state3_down; end end else if(switch2=b0) begin state3=state3_down; end else begin state3=state3_other; count3=39; end state3_other: if(switch2=b1) state30) begin count3=count3-1; if(switch2=b0&(state1=3b010|state2=3b010) begin light2=b0; state3=state3_down; end end else state3=state3_down; state3_down: begin light2=b0; count_3=3b0; state3=state3_start; end state3_up: begin light2=b1; state3=state3_work; end default: state3=state3_start; endcase endmodule測(cè)試程序timescale 100ns/10nsmodule test_light_All;reg clk10,rst;reg2:0 up,down;wire2:0 swh;wire2:0 li